Techniques for vertical FET gate length control

A method of forming a vertical field-effect transistor (VFET) device, the method comprising the steps of:

• patterning fins in a substrate;
• forming bottom source and drains at a base of the fins;
• forming bottom spacers on the bottom source and drains;
• forming first polymer spacers alongside opposite sidewalls of the fins, wherein the first polymer spacers comprise a monolayer of a first polymer brush material;
• forming second polymer spacers on the bottom source and drains offset from the fins by the first polymer spacers, wherein the second polymer spacers comprise a monolayer of a second polymer brush material that is un-grafted to the first polymer brush material;
• removing the first polymer spacers selective to the second polymer spacers creating a gap between the second polymer spacers and the fins;
• reflowing the second polymer spacers to close the gap;
• forming a cladding layer alongside the opposite sidewalls of the fins above the second polymer spacers;
• removing the second polymer spacers exposing the opposite sidewalls of the fins in between the bottom spacers and the cladding layer;
• forming gates along the opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers;
• forming top spacers above the cladding layer;
• and
• forming top source and drains above the top spacers.