Spacers for nanowire-based integrated circuit device and method of fabricating same

A method comprising:

• forming a semiconductor layer stack over a substrate, wherein the semiconductor layer stack includes at least one first semiconductor layer of a first semiconductor material and at least one second semiconductor layer of a second semiconductor material, the second semiconductor material being different than the first semiconductor material;
• forming a gate structure over a channel region of the semiconductor layer stack, wherein the gate structure includes a dummy gate stack;
• selectively removing the at least one first semiconductor layer from a source region and a drain region of the semiconductor layer stack;
• forming nanowire spacers in the source region and the drain region not underlying the gate structure, such that the at least one second semiconductor layer is disposed between the nanowire spacers in the source region and the drain region not underlying the gate structure;
• forming epitaxial source/drain features over the at least one second semiconductor layer and the nanowire spacers in the source region and the drain region not underlying the gate structure;
• removing the dummy gate stack to form an opening in the gate structure that exposes the semiconductor layer stack in the channel region;
• selectively removing the at least one first semiconductor layer from the channel region of the semiconductor layer stack;
• and
• forming a metal gate stack in the opening of the gate structure.

An integrated circuit device comprising:

• a nanowire disposed over a substrate;
• a gate structure traversing a portion of the nanowire, such that the gate structure separates a source region and a drain region of the nanowire, wherein a channel region of the nanowire is defined between the source region and the drain region;
• a nanowire spacer disposed adjacent to the nanowire, wherein the nanowire spacer spans an entirety of the source region and an entirety of the drain region, and further wherein a portion of the gate structure is disposed between the nanowire spacer;
• and
• an epitaxial source/drain feature disposed over the nanowire and the nanowire spacer in the source region and the drain region.