Silicon carbide MOSFET device and method for manufacturing the same

A method for manufacturing a silicon carbide MOSFET device, comprising forming a second gate oxide layer and a first gate oxide layer so as to form a gate oxide layer of the device, wherein a thickness of the second gate oxide layer is larger than a thickness of the first gate oxide layer;

• forming a JFET region, a channel, an N+ source region, and a P+ doped region that are adjacent to one another in sequence, forming a gate oxide layer medium for a first time, and removing one part of the gate oxide layer medium through etching so as to form the second gate oxide layer on the JFET region;
• forming a gate oxide layer medium for a second time on a region of a removed part of the gate oxide layer medium that is formed for the first time, wherein a thickness of the gate oxide layer medium formed for the second time is smaller than a thickness of the gate oxide layer medium formed for the first time;
• depositing polysilicon on the second gate oxide layer and the gate oxide layer medium formed for the second time;
• and
• etching the gate oxide layer medium and the polysilicon on the P+ doped region and one part of the N+ source region so as to form the first gate oxide layer and a polysilicon gate which covers the first gate oxide layer and the second gate oxide layer.

A method for manufacturing a silicon carbide MOSFET device, comprising steps of:

• S1:
• providing a silicon carbide substrate;
• S2:
• growing an N-type buffer layer on the silicon carbide substrate, wherein a thickness of the N-type buffer layer is in a range from 1 μm to 2 μm, and an N ion doping concentration thereof is in 1×1018 cm−3 order of magnitude;
• S3:
• growing an N-type epitaxial layer on the N-type buffer layer epitaxially, wherein a thickness of the N-type epitaxial layer is in a range from 10 μm to 13 μm, and an N ion doping concentration thereof is in a range from 1×1015 cm−3 to 9×1015 cm−3;
• S4:
• injecting Al ions into the N-type epitaxial layer to form a P well, wherein a junction depth of the P well is in a range from 0.5 μm to 1.0 μm, an Al ion peak doping concentration thereof is in a range from 1×1018 cm−3 to 5×1018 cm−3, a width of the P well is smaller than a width of the silicon carbide substrate, and a region that is arranged side by side with the P well on the N-type epitaxial layer is a JFET region;
• S5:
• injecting Al ions into the P well to form a P+ doped region, wherein a junction depth of the P+ doped region is in a range from 0.2 μm to 0.3 μm, and an Al ion doping concentration thereof is in a range from 1×1019 cm−3 to 5×1019 cm−3;
• S6:
• injecting N ions into a region of the P well adjacent to the P+ doped region to form an N+ source region, wherein a junction depth of the N+ source region is in a range from 0.2 μm to 0.3 μm, an N ion doping concentration thereof is in a range from 1×1019 cm−3 to 5×1019 cm−3, and forming a channel between the N+ source region and the JFET region;
• S7:
• forming SiO2 for a first time on the JFET region, the channel, the N+ source region, and the P+ doped region, wherein a thickness of the SiO2 is in a range from 80 nm to 240 nm, and the SiO2 is formed through a low pressure chemical vapor deposition technology, a wet thermal oxidation technology, or a dry thermal oxidation technology;
• S8:
• removing part of the SiO2 through etching to form a second gate oxide layer, wherein a ratio of a width of the second gate oxide layer to a width of the JFET region is in a range from 2:3 to 1:1;
• S9:
• forming SiO2 for a second time on one part of the JFET region, the channel, the N+ source region, and the P+ doped region except for the second gate oxide layer, wherein a thickness of the SiO2 is in a range from 40 nm to 80 nm, and the SiO2 is formed through a dry thermal oxidation technology at a temperature in a range from 1200° C. to 1350° C.;
• S10:
• depositing polysilicon on the SiO2, wherein a thickness of the polysilicon is in a range from 0.4 μm to 0.6 μm, and a P ion doping concentration thereof is in a range from 1×1020 cm−3 to 3×1020 cm−3;
• S11:
• removing SiO2 and polysilicon from the P+ doped region and one part of the N+ source region through etching to form a polysilicon gate pattern;
• S12:
• depositing an interlayer medium, and forming an ohmic contact hole through etching;
• S13:
• depositing Ni on the P+ doped region, one part of the N+ source region, and a back surface of the silicon carbide substrate, and performing annealing in an inert atmosphere at a temperature in a range from 800° C. to 1000° C., wherein a thickness of an Ni layer formed is in a range from 30 nm to 100 nm;
• and
• S14:
• depositing Al on the Ni layer, wherein a thickness of an Al layer formed is in a range from 1 μm to 3 μm.