Scaled memory structures or other logic devices with middle of the line cuts

A structure, comprising:

• a plurality of fin structures formed on a substrate;
• a plurality of gate structures spanning over adjacent fin structures of the plurality of fin structures;
• a cut in merged epitaxial source/drain regions which provides separate epitaxial source/drain regions for each of the plurality of gate structures;
• a cut in merged contact material formed adjacent to the plurality of gate structures, the cut resulting in separate contacts for each separate epitaxial source/drain regions;
• and
• dielectric material filling each of the cuts in the contact material and the epitaxial source/drain regions.