US 10,475,889 B1Granted

Gallium nitride power amplifier integration with metal-oxide-semiconductor devices

AssigneeQUALCOMM Incorporated

InventorsXia Li, Gengming Tao, Bin Yang

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Abstract

Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a semiconductor region disposed adjacent to the substrate, first fin(s) disposed adjacent to the semiconductor region, first gate region(s) disposed adjacent to the first fin(s), first drain contact(s) disposed above the first fin(s), first source contact(s) disposed below the substrate, a second fin disposed above the semiconductor region, and a second gate region, second source contact and second drain contact disposed adjacent to the second fin and above the semiconductor region. First path(s) are formed between the first drain contact(s) and the first source contact(s) for current flow(s) through the first fin(s) in a vertical direction along the first path(s). A second path is formed between the second source contact and the second drain contact for current flow through the second fin in a horizontal direction along the second path.

Claims19

Dependent claims

A semiconductor device comprising:

a substrate;
a semiconductor region disposed adjacent to the substrate;
at least one first fin disposed adjacent to the semiconductor region;
at least one first gate region disposed adjacent to the at least one first fin;
at least one first drain contact disposed above the at least one first fin;
at least one first source contact disposed below the substrate, wherein at least one first path is formed between the at least one first drain contact and the at least one first source contact for a first current flow through the at least one first fin in a vertical direction along the at least one first path;
a second fin disposed above the semiconductor region;
at least one second gate region disposed adjacent to the second fin;
and
a second source contact and a second drain contact disposed adjacent to the second fin and above the semiconductor region, wherein a second path is formed between the second source contact and the second drain contact for a second current flow through the second fin in a first horizontal direction along the second path.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/997,991Filed 5 Jun 2018
Published: US 2019/0371895 A15 Dec 2019
Granted: 12 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 62/8503
Being Group III-V materials, e.g. GaAs: nitride Group III-V materials, e.g. AlN or GaN
H03F 3/21
Power amplifiers, e.g. Class B amplifiers, Class C amplifiers: with semiconductor devices only
H10D 30/0241
Of fin field-effect transistors [FinFET]: doping of vertical sidewalls, e.g. using tilted or multi-angled implants
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]