Integrated circuit image sensor cell with skimming gate implemented using a vertical gate transistor structure
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorFrancois Roy
Life of this patent
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Abstract
An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.
Claims19
An imaging cell, comprising:
- a substrate doped with a first conductivity type;
- a skimming gate transistor coupled between a photosensitive charge node and an intermediate node, wherein the photosensitive charge node and intermediate node are regions within the substrate that are doped with a second conductivity type opposite the first conductivity type;
- and
- a transfer gate transistor coupled between the intermediate node and a sense node, wherein the sense node is a region within the substrate that is doped with the second conductivity type;
- wherein the skimming gate transistor includes a vertical gate electrode structure comprising:
- a first capacitive deep trench isolation extending into the substrate;
- and
- a second capacitive deep trench isolation extending into the substrate;
- wherein a channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations, wherein said channel is a region within the substrate that is doped with the second conductivity type;
- and
- wherein each capacitive deep trench isolation comprises a trench lined with an insulating liner and filled with a conductive or semiconductive material.
An integrated circuit, comprising:
- a semiconductor substrate doped with a first conductivity type;
- a photodiode having a doped charge generating region within the semiconductor substrate, wherein the doped charge generating region is doped with a second conductivity type opposite the first conductivity type;
- a skimming gate transistor including a doped channel region within the semiconductor substrate coupled between the doped charge generating region and a doped intermediate region, wherein the doped intermediate region and the doped channel region are both doped with the second conductivity type;
- and
- a transfer gate transistor coupled between the doped intermediate region and a doped sense region;
- wherein the skimming gate transistor includes a vertical gate electrode structure comprising:
- a first capacitive deep trench isolation extending into the semiconductor substrate;
- and
- a second capacitive deep trench isolation extending into the semiconductor substrate;
- wherein the doped channel region is positioned between the first and second capacitive deep trench isolations;
- and
- wherein each capacitive deep trench isolation comprises a trench lined with an insulating liner and filled with a conductive or semiconductive material.
An imaging cell, comprising:
- a skimming gate transistor coupled between a photosensitive charge node and an intermediate node;
- and
- a transfer gate transistor coupled between the intermediate node and a sense node;
- wherein the skimming gate transistor includes a vertical gate electrode structure comprising:
- a first capacitive deep trench isolation extending into a substrate;
- and
- a second capacitive deep trench isolation extending into the substrate;
- wherein a channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations;
- wherein each capacitive deep trench isolation comprises a trench lined with an insulating liner and filled with a conductive or semiconductive material;
- and
- wherein the trenches of the first and second capacitive deep trench isolations extend non-parallel to each other and non-parallel to a length of the channel of the skimming gate transistor.
Dependencies are inferred from the claim text.