TFT backplane and manufacturing method thereof

A manufacturing method of thin film transistor backplane, comprising the steps of:

• providing a substrate, forming a first metal layer on the substrate, and patterning the first metal layer to obtain a gate and a first metal electrode;
• forming a gate insulating layer on the substrate, the gate, and the first metal electrode, performing partial etching on the gate insulating layer with a dry etch process to obtain a TFT-related portion and a capacitor-related portion of the gate insulating layer that are respectively located on the gate and the first metal electrode, the capacitor-related portion of the gate insulating layer being formed by being partially etched off so as to have a reduced thickness that is less than a thickness of the TFT-related portion of the gate insulating layer;
• and
• forming an etch stop layer (ESL) on the gate insulating layer such that a capacitor-related part of the ESL is located on the capacitor-related portion of the gate insulating layer having the reduced thickness, forming a second metal layer on the capacitor-related part of the ESL, patterning the second metal layer to obtain a second metal electrode,
• wherein the gate insulating layer is formed of two non-metal films stacked on each other, wherein the TFT-related portion of the gate insulating layer comprises the two non-metal films stacked on the gate and the capacitor-related portion of the gate insulating layer is partially etched to remove one of the two non-metal films stacked on each other so as to comprise a single non-metal film stacked on the first metal electrode, wherein a top surface of the capacitor-related portion of the gate insulating layer on the first metal electrode is recessed and lower than a top surface of the TFT-related portion of the gate insulating layer on the gate.