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US 10,475,814 B2Granted
Ferroelectric memory devices
AssigneeSK hynix Inc.
InventorsHyangkeun Yoo, Joong Sik Kim
Life of this patent
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Abstract
A ferroelectric memory device includes a substrate, an interfacial insulation layer disposed on the substrate, a recombination induction layer disposed on the interfacial insulation layer, a ferroelectric layer disposed on the recombination induction layer, and a gate electrode disposed on the ferroelectric layer. The recombination induction layer includes a material containing holes acting as a majority carrier.
Claims20
A ferroelectric memory device comprising:
- a substrate;
- an interfacial insulation layer disposed on the substrate;
- a recombination induction layer disposed on the interfacial insulation layer;
- a ferroelectric layer disposed on the recombination induction layer;
- and
- a gate electrode disposed on the ferroelectric layer;
- and
- a source region and a drain region disposed in the substrate and spaced apart from each other,
- wherein the recombination induction layer includes a material containing holes acting as a majority carrier, and
- wherein the recombination induction layer is electrically isolated from the source region and the drain region.
7 more elements
A ferroelectric memory device comprising:
- a semiconductor substrate;
- a material layer disposed on the semiconductor substrate, wherein the material layer contains holes as a majority carrier;
- a ferroelectric layer disposed on the material layer;
- a gate electrode disposed on the ferroelectric layer;
- and
- a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other,
- wherein the material layer is disposed on the semiconductor substrate between the source region and the drain region, and
- wherein the recombination induction layer is electrically isolated from the source region and the drain region.
5 more elements
A ferroelectric memory device comprising:
- a silicon substrate doped with P-type impurities;
- a silicon oxide layer disposed on the silicon substrate;
- a semiconductor layer disposed on the silicon oxide layer and doped with P-type impurities acting as a dopant;
- a ferroelectric layer disposed on the semiconductor layer;
- a gate electrode disposed on the ferroelectric layer;
- and
- a source region and a drain region disposed in the silicon substrate to be spaced apart from each other,
- wherein the silicon oxide layer is disposed on the silicon substrate between the source region and the drain region,
- wherein the semiconductor layer is configured to combine holes created by the dopant with electrons from the silicon substrate injected into the semiconductor layer, and
- wherein the recombination induction layer is electrically isolated from the source region and the drain region.
7 more elements
Dependencies are inferred from the claim text.