Ferroelectric memory device and method of manufacturing the same
AssigneeSK hynix Inc.
InventorHyangkeun Yoo
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AssigneeSK hynix Inc.
InventorHyangkeun Yoo
Estimating the term…
In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region. The ferroelectric memory device includes a ferroelectric superlattice structure disposed on the substrate and having at least two kinds of different dielectric layers alternately stacked. Further, the ferroelectric memory device includes a gate electrode layer disposed on the superlattice structure.
A ferroelectric memory device comprising:
A method of manufacturing a ferroelectric memory device comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the memory core region
Insulated-gate field-effect transistors [IGFET]: iGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs
Characterised by the conductor: the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
Characterised by the conductor: the conductor comprising a layer of alloy material, compound material or organic material contacting the…
About 11 years 1 month of term left · ends 21 Nov 2037 (estimated)
The present application claims priority under 35 U.S.C. 119(a) to Korean Patent Application No. 10-2017-0024300, filed on Feb. 23, 2017, which is herein incorporated by reference in its entirety.
Embodiments of the present disclosure relate to a ferroelectric memory device and a method of manufacturing the same.
In general, a ferroelectric material is a material having spontaneous electrical polarization in the absence of an applied external electric field. More specifically, a ferroelectric material can maintain one of two stable remanent polarization states. Thus, a ferroelectric material may be utilized to store digital information in a nonvolatile manner. For example, binary information “0” or “1” may be stored in remanent polarization states.
FIG. 1 is a schematic view illustrating a ferroelectric memory device according to an embodiment of the present disclosure.
FIG. 2 is a schematic view illustrating a ferroelectric memory device according to an embodiment of the present disclosure.
FIG. 3 is a schematic view illustrating a ferroelectric memory device according to an embodiment of the present disclosure
Various embodiments will now be described hereinafter with reference to the accompanying drawings. In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. The drawings are described with respect to an observer's viewpoint. If a first element is referred to as located on a second element, it may be understood that the first element is directly located on the second element; that an additional element may be interposed between the first element and the second element; or that a portion of the first element is directly located on a portion of the second element. The same reference numerals may refer to the same elements throughout the specification.
In addition, expression of a singular form of a word includes the plural forms of the word unless clearly used otherwise in the context of the disclosure. The terms “comprise” or “have” are intended to specify the presence of a feature, a number, a step, an operation, an element, a component, a part, or combinations thereof, but neither term precludes the presence or possibility of the addition of one or more other features, numbers, steps, operations, elements, components, parts, or combinations thereof. Further, each step or process in a method or a manufacturing method need not be performed in any order set forth in the disclosure unless a specific sequence is explicitly described. In other words, each step or process in a method or manufacturing method disclosed herein may be performed sequentially in the stated order, may be performed out of sequence from the stated order, or may be performed substantially at the same time as one or more other steps or processes. The steps or processes may also be performed in a reverse order.
An embodiment of the present disclosure includes a ferroelectric memory device having a ferroelectric superlattice structure. Techniques for developing or inducing ferroelectric properties in paraelectric materials have been reported in recent research. As an example, it has been reported that, in a thin film fabricating process, when anisotropic stress is applied to a thin non-ferroelectric hafnium oxide film, a lattice structure is transformed from a tetragonal crystal system to an orthorhombic crystal system, forming a hafnium oxide layer having ferroelectric properties. By way of non-limiting examples, anisotropic stress may be produced through doping with dopants, surface energy effects, and thin film growth mechanisms in relation to a hafnium oxide layer. J. Müller, et al. (Nano Lett., 2012, 12 (8), pp 4318-4323) has disclosed that in a solid solution of HfxZryO2 (0<x, y<1) including hafnium oxide (HfO2) and zirconium oxide (ZrO2), when the content ratio of hafnium (Hf) and zirconium (Zr) constituting the hafnium oxide (HfO2) and the zirconium oxide (ZrO2) is controlled, the HfxZryO2 solid solution can have a structure of four-crystal system that has ferroelectric properties.