US 10,475,809 B2Granted

Semiconductor memory device

AssigneeToshiba Memory Corporation

InventorsTakamasa Ito, Toshiaki Fukuzumi

Life of this patent

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Abstract

A semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and extending in the first direction, a third electrode layer above the first electrode layer and extending in the first direction, an insulating member between the second and third electrode layers and extending in the first direction, first semiconductor members extending in the second direction through the first and second electrodes, second semiconductor members extending in the second direction through the first and third electrode layers, and third semiconductor members extending in the second direction, each having a first portion between the second and third electrode layers and in contact with the insulating member, and a second portion extending through the first electrode layer. In the first direction, an arrangement density of the third semiconductor members is lower than that of the first or second semiconductor member.

Claims17

Dependent claims

A semiconductor memory device, comprising:

a first electrode layer extending in a first direction;
a second electrode layer separated in a second direction from the first electrode layer, the second direction intersecting the first direction, the second electrode layer extending in the first direction;
a third electrode layer separated in the second direction from the first electrode layer, the third electrode layer extending in the first direction;
an insulating member between the second electrode layer and the third electrode layer, and extending in the first direction;
first semiconductor members extending through the first electrode layer and the second electrode layer;
second semiconductor members extending through the first electrode layer and the third electrode layer;
and
third semiconductor members extending in the second direction, each having a first portion that is between the second electrode layer and the third electrode layer and in contact with the insulating member, and a second portion that extends through the first electrode layer,
wherein, in the first direction, an arrangement density of the third semiconductor members is lower than those of the first semiconductor members and the second semiconductor members.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/693,433Filed 31 Aug 2017
Priority: JP 2016-2178858 Nov 2016
Published: US 2018/0130820 A110 May 2018
Granted: 12 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10W 20/435
Characterised by their conductive parts: cross-sectional shapes or dispositions of interconnections