Method for making non-volatile memory device
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsAnson Heryanto, Eng Huat Toh, Yongshun Sun, Yoke Leng Lim, Siow Lee Chwa
Life of this patent
Estimating the term…
Abstract
Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.
Claims20
A method comprising:
- forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG,
- forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell;
- and
- implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.
A method comprising:
- forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical inter-poly oxide (IPO) layer is formed between the SG and the CG and FG,
- forming a dielectric layer between the CG and FG;
- forming an etching mask over the control gate;
- forming and patterning an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell;
- implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.
A method comprising:
- forming a first polysilicon gate layer over a substrate;
- etching the first polysilicon gate layer to form a floating gate (FG) over the substrate;
- consecutively forming a dielectric layer, an second polysilicon gate layer and hard mask (HM) and patterning to form a control gate (CG) over the FG with the dielectric formed between the FG and CG and the HIM formed over the CG;
- forming an inter polysilicon oxide (IPO) on sides of the FG and CG;
- forming a third polysilicon gate layer and etching to form a SG on a first side of the FG and CG;
- forming an implant mask over a portion of the SG, CG and IPO;
- and
- implanting dopants into the substrate using the implant mask to form a source drain (S/D) region.
Dependencies are inferred from the claim text.