Method of forming an array of capacitors, a method of forming DRAM circuitry, and a method of forming an elevationally-elongated conductive structure of integrated circuitry

A method of forming DRAM circuitry comprising:

• providing a substrate comprising pairs of recessed access devices, the recessed access devices individually comprising:
• a conductive gate in a trench in semiconductive material;
• a gate insulator along sidewalls and a base of the trench between the conductive gate and the semiconductive material;
• a pair of source/drain regions in upper portions of the semiconductive material on opposing sides of the trench;
• a channel region in the semiconductive material below the pair of source/drain regions along the trench sidewalls and around the trench base;
• and
• one of the source/drain regions of the pair of source/drain regions in individual of the pairs of recessed access devices being laterally between the conductive gates in and being shared by the individual pairs of recessed access devices, the others of the source/drain regions of the pair of source/drain regions not being shared in the individual pairs of recessed access devices;
• forming digitline structures that are individually directly electrically coupled to the one shared source/drain region of multiple of the individual pairs of recessed access devices;
• forming conductive vias laterally between and spaced longitudinally along the digitline structures, individual of the conductive vias being directly electrically coupled to one of the other source/drain regions in the individual pairs of recessed access devices, the individual conductive vias having an upper horizontal perimeter;
• forming masking material directly above the digitline structures and the conductive vias;
• forming an opening in the masking material directly above individual of the upper horizontal perimeters of individual of the conductive vias, individual of the masking-material openings comprising a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below, the individual masking-material openings comprising an upper horizontal perimeter having at least some portion that is outward of the upper horizontal perimeter of the conductive via directly there-below;
• forming conductive material in the individual masking-material openings against sidewalls of the individual masking-material openings and directly against the conductive via directly there-below, an upper horizontal perimeter of the conductive material in the individual masking-material openings extending outwardly beyond the upper horizontal perimeter of the conductive via directly there-below;
• and
• forming a plurality of capacitors individually comprising a lower conductive electrode, an upper conductive electrode, and a capacitor insulator there-between;
• individual of the lower conductive electrodes comprising the conductive material in the individual masking-material openings.