Capacitor cell and structure thereof

A capacitor cell structure, comprising:

• a semiconductor substrate, having a first conductive type;
• a first well region on the semiconductor substrate, having a second conductive type;
• a first source region in the first well region and coupled to a first power line;
• a first drain region in the first well region;
• a first active region between the first source region and the first drain region in the first well region;
• a second well region on the semiconductor substrate, having the first conductive type;
• a second source region in the second well region and coupled to a second power line;
• a second drain region in the second well region and coupled to the first active region;
• a second active region between the second source region and the second drain region in the second well region and coupled to the first drain region;
• a first doped region in the first well region and coupled to the second drain region, having the first conductive type;
• a third active region between the first doped region and the first drain region or between the first doped region and the first source region in the first well region and coupled to the second drain region;
• a second doped region in the second well region and coupled to the first drain region, having the second conductive type;
• and
• a fourth active region between the second doped region and the second drain region or between the second doped region and the second source region in the second well region and coupled to the first drain region.

A capacitor cell structure, comprising:

• a semiconductor substrate;
• an N-type well region on the semiconductor substrate;
• a plurality of PMOS transistors, each of the PMOS transistors comprises a first source region, a first drain region, and a first active region between the first source region and the first drain region in the N-type well region, wherein the first source regions and the first drain regions are interlaced to form a first row;
• a P-type well region on the semiconductor substrate;
• and
• a plurality of NMOS transistors, each of the NMOS transistors comprises a second source region, a second drain region, and a second active region between the second source region and the second drain region in the P-type well region, wherein the second source regions and the second drain regions are interlaced to form a second row,
• wherein the first source regions of a first group of the PMOS transistors are coupled to a power line, and the second source regions of a first group of the NMOS transistors are coupled to a ground,
• wherein the first active regions of the PMOS transistors are coupled to the second drain regions of the first group of the NMOS transistors, and the second active regions of the NMOS transistors are coupled to the first drain regions of the first group of the PMOS transistors,
• wherein the first drain regions of a second group of the PMOS transistors are coupled to the second active regions or the second drain regions of the first group of the NMOS transistors, and the first source regions of the second group of the PMOS transistors are coupled to the second drain regions of the first group of the NMOS transistors or the power line,
• wherein the second drain regions of a second group of the NMOS transistors are coupled to the first active regions or the first drain regions of the first group of the PMOS transistors, and the second source regions of the second group of the NMOS transistors are coupled to the first drain regions of the first group of PMOS transistors or the ground.