Fin field effect transistor (FinFET) device structure with capping layer and method for forming the same

A fin field effect transistor (FinFET) device structure, comprising:

• a fin structure formed over a substrate;
• a first gate structure formed over the fin structure, wherein the first gate structure has a first width;
• a second gate structure formed over the fin structure, wherein the second gate structure has a second width, and the first width is greater than the second width;
• an inter-layer dielectric (ILD) layer formed adjacent to the first gate structure and the second gate structure;
• a first capping layer formed over the first gate structure, wherein the first capping layer is in direct contact with a top surface of the first gate structure;
• and
• a second capping layer formed over the second gate structure, wherein the second capping layer is in direct contact with a top surface of the second gate structure, and a first top surface of the first capping layer is higher than a second top surface of the second capping layer, and the second top surface of the second capping layer is higher than a third top surface of the ILD layer.

A method for forming a fin field effect transistor (FinFET) device structure, comprising:

• forming a fin structure over a substrate, wherein the substrate comprises a first region and a second region;
• forming a first gate structure over the fin structure in the first region, wherein the first gate structure has a first width;
• forming a second gate structure over the fin structure in the second region, wherein the second gate structure has a second width, and the first width is greater than the second width;
• forming a first capping layer and a second capping layer over the first gate structure and the second gate structure respectively, wherein a top surface of the first capping layer is higher than a top surface of the second capping layer;
• and
• forming a first etching stop layer and a second etching stop layer over the first capping layer and the second capping layer, respectively, wherein a sidewall surface of the first capping layer is in direct contact with the first etching stop layer.