Packaged semiconductor device

A method of fabricating a packaged semiconductor device, comprising:

• providing a multi-layer molded interconnect substrate (MIS) having a signal layer including first and second traces for a first channel and first and second traces for a second channel on a dielectric layer with vias, and a bottom metal layer under the dielectric layer for providing a ground return path, the signal layer including contact pads, wherein the first and second traces of the first and second channel include narrowed trace regions and the bottom metal layer comprises a patterned layer including a plurality of ground cut regions;
• attaching a first and a second direct current (DC) blocking capacitor in series within the first and second traces of the first channel for providing alternating current (AC) coupling, the first and second DC blocking capacitors each with one plate over one of the ground cuts and a third and a fourth DC blocking capacitor in series within the first and second traces of the second channel for providing AC coupling, the third and fourth DC blocking capacitors each with one plate over one of the ground cuts, and
• attaching an integrated circuit (IC) including a first differential input channel coupled to receive an output from the first and second DC blocking capacitors and at least a second differential input channel coupled to receive an output of the third and fourth DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.