ESD protection diode and electronic device including the same

An electronic device comprising:

• a first voltage terminal configured to receive a power supply voltage;
• an input/output terminal configured to receive an input voltage;
• a second voltage terminal grounded;
• and
• an Electrostatic Discharge (ESD) protection diode configured to form a discharge path when an ESD pulse is received from the first voltage terminal, the input/output terminal, and the second voltage terminal,
• wherein the ESD protection diode forms a first discharge path from the first voltage terminal to the input/output terminal when a voltage level of the first voltage terminal is higher than a voltage level of the input/output terminal by more than a first reference value,
• wherein the ESD protection diode forms a second discharge path from the input/output terminal to the first voltage terminal when the voltage level of the input/output terminal is higher than the voltage level of the first voltage terminal by more than a second reference value,
• wherein the ESD protection diode forms a third discharge path from the input/output terminal to the second voltage terminal when the voltage level of the input/output terminal is higher a voltage level of the second voltage terminal by more than a third reference value,
• wherein the ESD protection diode forms a fourth discharge path from the second voltage terminal to the input/output terminal when the voltage level of the second voltage terminal is higher than the voltage level of the input/output terminal by more than a fourth reference value,
• wherein the ESD protection diode includes:
• a base substrate;
• a first well disposed on the base substrate and connected to the first voltage terminal;
• a second well disposed on the base substrate and connected to the second voltage terminal;
• a third well disposed on the base substrate and connected to the input/output terminal;
• a fourth well disposed between the first well and the third well;
• and
• a fifth well disposed between the second well and the third well,
• wherein the first well comprises a first N+ diffusion region formed spaced apart from the first voltage terminal,
• the second well comprises a second N+ diffusion region formed spaced part from the second voltage terminal,
• the fourth well comprises a first P+ diffusion region,
• the fifth well comprises a second P+ diffusion region,
• the first well, the second well, and the third well are N-type wells and the fourth well and the fifth well are P-type wells,
• the first well further comprises a third N+ diffusion region and a third P+ diffusion region which are formed to be connected to the first voltage terminal,
• the second well further comprises a fourth N+ diffusion region and a fourth P+ diffusion region, which are formed to be connected to the second voltage terminal, and
• the third P+ diffusion region is formed between the first N+ diffusion region and the third N+ diffusion region and the fourth P+ diffusion region is formed between the second N+ diffusion region and the fourth P+ diffusion region.