Semiconductor package

A semiconductor package comprising:

• a first connecting layer comprising a first insulating layer and a plurality of first conductive patterns;
• a second connecting layer disposed below the first connecting layer, the second connecting layer comprising a second insulating layer and a plurality of second conductive patterns;
• a third connecting layer disposed between the first connecting layer and the second connecting layer, the third connecting layer comprising a third insulating layer and a plurality of third conductive patterns;
• a plurality of inter-package connecting members each of which connects the third connecting layer and the first connecting layer;
• a plurality of inter-layer connecting members each of which extends between the third connecting layer and the second connecting layer;
• a plurality of memory chips on the first connecting layer;
• a controller chip on the second connecting layer;
• and
• a buffer chip on the third connecting layer,
• wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.

A semiconductor package comprising:

• a memory sub-package comprising a first connecting layer and a plurality of memory chips disposed on the first connecting layer;
• a logic sub-package comprising a second connecting layer, a controller chip on the second connecting layer, and a first buffer chip and a second buffer chip connected to the memory sub-package and the controller chip;
• a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package;
• and
• a plurality of external connecting members disposed beneath the second connecting layer,
• wherein the number of first data transfer lines between the first buffer chip and the memory sub-package is greater than the number of second data transfer lines between the first buffer chip and the controller chip, and the number of third data transfer lines between the second buffer chip and the memory sub-package is greater than the number of fourth data transfer lines between the second buffer chip and the controller chip.