Seal-ring structure for stacking integrated circuits

An integrated circuit (IC) die comprising:

• a first substrate and second substrate;
• an interconnect structure between the first and second substrates, wherein the interconnect structure comprises a plurality of wires and a plurality of vias, and wherein the wires and the vias are stacked;
• a seal-ring structure in the interconnect structure, wherein the seal-ring structure is defined in part by the wires and the vias and extends from adjacent the first substrate to adjacent the second substrate;
• a pad structure over the first and second substrates;
• and
• a through substrate via (TSV) extending through the second substrate from direct contact with the pad structure to direct contact with the seal-ring structure.

A method for forming a three-dimensional (3D) integrated circuit (IC) die, the method comprising:

• forming a first IC die comprising a first substrate, and further comprising a first seal-ring structure on the first substrate;
• forming a second IC die comprising a second substrate, and further comprising a second seal-ring structure on the second substrate;
• bonding the second IC die to the first IC die, such that the first and second seal-ring structures are between the first and second substrates;
• forming a passivation layer on the second substrate;
• and
• forming a pad structure overhanging the passivation layer and protruding through the passivation layer to the second substrate at a location directly over the first and second seal-ring structures.