Electronic device
AssigneeKabushiki Kaisha Toshiba
InventorYoichiro Kurita
Life of this patent
Estimating the term…
Abstract
According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
Claims14
An electronic device, comprising:
- a first chip including a first conductive member, a first region, and a second region;
- a second chip including a second conductive member, a third region, and a fourth region;
- a third chip including a third conductive member, a fifth region, and a sixth region;
- a first terminal;
- a second terminal;
- and
- an interconnect layer provided between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the fifth region of the third chip, between the first terminal and the fourth region of the second chip, and between the second terminal and the sixth region of the third chip,
- the interconnect layer including
- a fourth conductive member provided between the first region of the first chip and the third region of the second chip, the fourth conductive member connecting the first conductive member of the first chip and the second conductive member of the second chip, and
- a fifth conductive member provided between the second region of the first chip and the fifth region of the third chip, the fifth conductive member connecting the first conductive member of the first chip and the third conductive member of the third chip,
- the first chip being provided between the first terminal and the second terminal, and being an electrical interconnect member connecting the second chip and the third chip via the first conductive member, the fourth conductive member, and the fifth conductive member.
An electronic device, comprising:
- a first chip including a first conductive member, a first region, and a second region;
- a second chip including a second conductive member, a third region, and a fourth region;
- a third chip including a third conductive member, a fifth region, and a sixth region;
- a first terminal;
- a second terminal;
- and
- an interconnect layer provided between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the fifth region of the third chip, between the first terminal and the fourth region of the second chip, and between the second terminal and the sixth region of the third chip,
- the interconnect layer including
- a fourth conductive member provided between the first region of the first chip and the third region of the second chip, the fourth conductive member connecting the first conductive member of the first chip and the second conductive member of the second chip, and
- a fifth conductive member provided between the second region of the first chip and the fifth region of the third chip, the fifth conductive member connecting the first conductive member of the first chip and the third conductive member of the third chip,
- the first chip being provided between the first terminal and the second terminal, and including a first memory element connected to the fourth conductive member, and
- the third chip including a second memory element connected to the fifth conductive member.
Dependencies are inferred from the claim text.