Semiconductor package structure and method of making the same

A semiconductor package structure, comprising:

• a substrate, having a top surface and a bottom surface, the substrate comprising a plurality of inner connection pads and a plurality of outer connection pads, the inner connection pads and the outer connection pads being individually disposed on the top surface and the bottom surface of the substrate;
• a chip, disposed on the top surface of the substrate;
• a plurality of bumps, electrically connected to the chip and the inner connection pads of the substrate;
• an encapsulation layer, covering the bumps, the chip and the top surface of the substrate, the encapsulation layer having a top surface and at least one side surface;
• and
• a thermal expansion-matching layer, covering the whole top surface of the encapsulation layer, and exposing the at least one side surface of the encapsulation layer, wherein the thermal expansion coefficient of the thermal expansion-matching layer is different from the thermal expansion coefficient of the encapsulation layer, wherein the encapsulation layer comprises a first epoxy molding compound (EMC), the thermal expansion-matching layer comprises a second EMC, the first and the second EMCs both comprise silicone, epoxy, hardener and flame retardant, and a composition ratio of the first EMC is different from a composition ratio of the second EMC.