Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorSunchul Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a first semiconductor chip on a first substrate, a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip, a solder structure provided on the first substrate, and a second substrate provided on the solder structure. A guide receptacle is formed at one of a top surface of the first mold layer and a bottom surface of the second substrate, a first alignment protrusion is formed at the other of the top surface of the first mold layer and the bottom surface of the second substrate, and at least a portion of the first alignment protrusion is provided in the guide receptacle.
Claims19
A semiconductor package, comprising:
- a first semiconductor chip on a first substrate;
- a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip;
- a solder structure provided on the first substrate;
- and
- a second substrate provided on the solder structure, wherein:
- a guide receptacle is formed at one of a top surface of the first mold layer and a bottom surface of the second substrate,
- a first alignment protrusion is formed at the other of the top surface of the first mold layer and the bottom surface of the second substrate and consists of an electrically insulating material composition, and
- at least a portion of the first alignment protrusion is provided in the guide receptacle.
A semiconductor package, comprising:
- a first substrate;
- a first semiconductor chip on the first substrate;
- a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip, the first mold layer comprising a first guide portion formed in a top surface thereof;
- solder structures provided on the first substrate;
- and
- an interposer substrate provided on the solder structures and spaced apart from the first semiconductor chip,
- wherein the interposer substrate comprises a first insulating protruding portion provided on a bottom surface thereof, and
- at least a portion of a side surface of the first insulating protruding portion faces a side surface of the first guide portion,
- wherein the first guide portion is defined by a trench, and the first mold layer further comprises a second guide portion defined by the trench, and
- wherein the second guide portion is provided between an outer side surface of the first substrate and an outermost one of the solder structures, when viewed in a plan view.
A semiconductor package, comprising:
- a first semiconductor chip on a first substrate;
- a first mold layer covering a side surface of the first semiconductor chip, the first mold layer having a first top surface and a second top surface, which is located at a level lower than the first top surface;
- a solder structure provided on the first substrate;
- and
- a second substrate provided on the solder structure,
- wherein the second substrate comprises a first insulating protruding portion provided on a bottom surface thereof,
- a bottom surface of the first insulating protruding portion is located at a level, which is lower than the first top surface of the first mold layer and is equal to or higher than the second top surface of the first mold layer, and
- the first insulating protruding portion is spaced apart from the solder structure and the first semiconductor chip when viewed in a plan view, and wherein:
- the second substrate further comprises a second insulating protruding portion provided on the bottom surface thereof,
- the second insulating protruding portion overlaps the first semiconductor chip, when viewed in a plan view, and
- the first insulating protruding portion has a thickness in a vertical direction greater than that of the second insulating protruding portion.
Dependencies are inferred from the claim text.