Fan-out semiconductor package

A fan-out semiconductor package comprising:

• a frame including a plurality of insulating layers, a plurality of wiring layers each disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion on a first surface of the frame;
• a semiconductor chip, disposed in the recess portion, having an active surface, on which connection pads are disposed, and an inactive surface opposing the active surface;
• a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion;
• an electronic component;
• a second encapsulant covering at least portions of the electronic component;
• and
• a connection member disposed on the first surface of the frame and the active surface of the semiconductor chip, and including one or more redistribution layers,
• wherein the connection pads of the semiconductor chip and the electronic component are electrically connected to each other through the plurality of wiring layers of the frame and the one or more redistribution layers of the connection member,
• wherein the recess portion has one surface covered with a stopper layer and another surface opposing the one surface being opened,
• wherein the electronic component is directly connected to the plurality of wiring layers of the frame through metal bumps, and
• wherein at least one of the plurality of wiring layers is disposed on a same level as the stopper layer.

A fan-out semiconductor package comprising:

• a frame including a plurality of insulating layers, a plurality of wiring layers each disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion having a stopper layer beneath a top surface thereof;
• a semiconductor chip having an active surface, on which connection pads are disposed, and an inactive surface opposing the active surface, the semiconductor chip being disposed on a first surface of the frame and disposed in the recess portion so that the inactive surface is connected to the stopper layer;
• a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion;
• an electronic component;
• a second encapsulant covering at least portions of the electronic component;
• a connection member disposed on the first surface of the frame and the active surface of the semiconductor chip, and including one or more redistribution layers;
• a first passivation layer disposed beneath the connection member and having openings exposing at least portions of the one or more redistribution layers;
• underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed one or more redistribution layers;
• and
• electrical connection structures disposed beneath the first passivation layer and connected to the underbump metal layers,
• wherein the connection pads of the semiconductor chip and the electronic component are electrically connected to each other through the plurality of wiring layers of the frame and the one or more redistribution layers of the connection member.