Multi-threshold voltage semiconductor device

A semiconductor device, comprising:

• a first metal-oxide semiconductor (MOS) transistor on a substrate;
• a first ferroelectric (FE) layer connected to the first MOS transistor, wherein the first FE layer is overlapped by a first gate electrode of the first MOS transistor entirely;
• a first buffer layer under and directly contacting the first FE layer, wherein a width of the first FE layer is greater than a width of the first buffer layer;
• a second MOS transistor on the substrate;
• a second FE layer connected to the second MOS transistor, wherein the first FE layer and the second FE layer comprise different capacitance and different widths and the second FE layer is overlapped by a second gate electrode of the second MOS transistor entirely;
• and
• a second buffer layer under and directly contacting the second FE layer, wherein a width of the second FE layer is greater than a width of the second buffer layer.