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US 10,475,732 B2Granted
3DIC package integration for high-frequency RF system
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWen-Shiang Liao
Life of this patent
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Abstract
A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.
Claims20
A device, comprising:
- a silicon oxide layer that is a one-layer structure with no metal ingredients and no additives including potassium oxide (K2O) or sodium oxide (Na2O);
- a plurality of conductive through vias (TVs) that are filled with a conductive material and that penetrate through the silicon oxide layer;
- a plurality of conductive elements embedded in a bottom surface of the silicon oxide layer and interconnecting a first portion of the conductive TVs by contacting peripheral portions of the first portion of the conductive TVs;
- a plurality of redistribution lines (RDLs) on a top surface of the silicon oxide layer and interconnecting the first portion of the conductive TVs, wherein the RDLs, the first portion of the conductive TVs, and the conductive elements form an inductor and an interface between each of the RDLs and the first portion of the conductive TVs is coplanar with the top surface of the silicon oxide layer;
- and
- an under bump metallurgy (UBM) layer contacting a bottom surface of a second portion of the conductive TVs, wherein an interface between the UBM layer and the second portion of the conductive TVs is substantially coplanar with the bottom surface of the silicon oxide layer.
3 more elements
A device, comprising:
- a silicon oxide layer that is a one-layer structure with no metal ingredients and no additives including potassium oxide (K2O) or sodium oxide (Na2O);
- a plurality of conductive through vias (TVs) that are filled with a conductive material and that penetrate through the silicon oxide layer;
- a plurality of conductive elements embedded in a bottom surface of the silicon oxide layer and interconnecting a first portion of the conductive TVs by contacting peripheral portions of the first portion of the conductive TVs;
- a plurality of redistribution lines (RDLs) on a top surface of the silicon oxide layer and interconnecting the first portion of the conductive TVs, wherein the RDLs, the first portion of the conductive TVs, and the conductive elements form an inductor;
- a plurality of interconnects electrically coupled or connected to the plurality of the RDLs;
- a polymer insulating layer covering a top surface of the RDLs, the interconnects, the top surface of the silicon oxide layer, and a top surface of the first portion of the conductive TVs;
- and
- an under bump metallurgy (UBM) layer contacting a bottom surface of a second portion of the conductive TVs, wherein an interface between the UBM layer and the second portion of the conductive TVs is substantially coplanar with the bottom surface of the silicon oxide layer.
5 more elements
A device, comprising:
- a silicon oxide layer that is a one-layer structure with no metal ingredients and no additives including potassium oxide (K2O) or sodium oxide (Na2O);
- a plurality of conductive through vias (TVs) that are filled with a conductive material and that penetrate through the silicon oxide layer;
- a plurality of conductive elements embedded in a bottom surface of the silicon oxide layer and interconnecting a first portion of the conductive TVs by contacting peripheral portions of the first portion of the conductive TVs;
- a plurality of redistribution lines (RDLs) on a top surface of the silicon oxide layer and interconnecting the first portion of the conductive TVs, wherein the RDLs, the first portion of the conductive TVs, and the conductive elements form an inductor and an interface between each of the RDLs and the first portion of the conductive TVs is coplanar with the top surface of the silicon oxide layer;
- a polymer insulating layer covering a top surface of the RDLs;
- a plurality of active or passive electronic devices over or in the silicon oxide layer;
- a plurality of interconnects in the polymer insulating layer and electrically coupled or connected to the plurality of the RDLs;
- and
- an under bump metallurgy (UBM) layer contacting a bottom surface of a second portion of the conductive TVs, wherein an interface between the UBM layer and the second portion of the conductive TVs is substantially coplanar with the bottom surface of the silicon oxide layer.
6 more elements
Dependencies are inferred from the claim text.