Package with metal-insulator-metal capacitor and method of manufacturing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
Life of this patent
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Abstract
A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
Claims20
A method comprising:
- depositing a first polymer layer overlying a chip;
- forming a first interconnect structure and a second interconnect structure overlying the first polymer layer and electrically coupled to the chip;
- depositing a second polymer layer overlying the first and second interconnect structures;
- patterning the second polymer layer to form a first opening and a second opening respectively exposing the first and second interconnect structures;
- forming a capacitor lining the first opening and overlying the second polymer layer;
- depositing a barrier layer overlying and lining the capacitor and the second opening;
- forming a first conductive under-bump structure and a second conductive under-bump structure on the barrier layer, respectively at the capacitor and the second interconnect structure;
- performing an etch into the barrier layer using the first and second conductive under-bump structures as a mask;
- and
- forming a conductive bump on the second conductive under-bump structure.
A method comprising:
- depositing a first polymer layer overlying an integrated circuit (IC) chip and a molding structure surrounding the IC chip;
- forming a first interconnect structure and a second interconnect structure overlying the first polymer layer and electrically coupled to the IC chip;
- depositing a second polymer layer overlying the first and second interconnect structures;
- performing a first etch into the second polymer layer to form a first opening and a second opening respectively exposing the first and second interconnect structures;
- depositing a first conductive layer overlying the second polymer layer;
- performing a second etch into the first conductive layer to form a lower capacitor electrode lining the first opening;
- forming a capacitor dielectric layer and an upper capacitor electrode stacked on the lower capacitor electrode after and independent of formation of the lower capacitor electrode;
- and
- forming a first under-bump metallization (UBM) structure and a second UBM structure respectively overlying and conforming to the upper capacitor electrode and the second opening.
A method comprising:
- depositing a first polymer layer overlying a chip;
- forming a first redistribution layer (RDL), a second RDL, and a third RDL overlying the first polymer layer and electrically coupled to the chip;
- depositing a second polymer layer overlying the first, second, and third RDLs;
- patterning the second polymer layer to form a first RDL opening, a second RDL opening, and a third RDL opening respectively exposing the first, second, and third RDLs;
- forming a capacitor overlying the first RDL and in the first RDL opening;
- forming a mask having a first mask opening overlying the capacitor and the third RDL, and further having a second mask opening overlying the second RDL;
- depositing a first conductive layer having a first conductive segment and a second conductive segment that are independent and respectively in the first and second mask openings, wherein the first conductive segment extends from overlying and electrically coupled to the capacitor to overlying and electrically coupled to the third RDL;
- removing the mask;
- and
- forming an isolation coating covering the first conductive segment and defining an isolation opening exposing the second conductive segment.
Dependencies are inferred from the claim text.