US 10,475,706 B2 · Making a defect free fin based device in lateral epitaxy overgrowth region

Abstract

Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.

Claims18

Dependent claims

An integrated circuit structure, comprising:

a first insulating layer above a substrate, the first insulating layer having a top and a sidewall;
a semiconductor fin on the first insulating layer, the semiconductor fin having a top, a first sidewall and a second sidewall, the first sidewall substantially co-planar with the sidewall of the first insulating layer, and the second sidewall opposite the first sidewall;
and
a second insulating layer having a first portion adjacent to the sidewall of the first insulating layer and adjacent a lower portion of the first sidewall of the semiconductor fin, and the second insulating layer having a second portion on the top of the first insulating layer and adjacent a lower portion of the second sidewall of the semiconductor fin.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

15/430,348Filed 10 Feb 2017 · continuation

Published

US 2017/0154981 A11 Jun 2017

Granted

12 Nov 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 84/0128
The components including insulated gates, e.g. IGFETs: manufacturing their channels
H10D 84/0158
The components including insulated gates, e.g. IGFETs: the components including FinFETs

Family

PCT/US2013/048776Parent of this continuation · filed 28 Jun 2013

US 2017/0154981 A1Pre-grant publication · published 1 Jun 2017

Application14/777,730Parent of this continuation

US 9,583,396 B2Parent of this continuation

US 2016/0204036 A1Published application

US 10,475,706 B2This patent

From the US filing history. Foreign family members aren’t listed.

Making a defect free fin based device in lateral epitaxy overgrowth region

Life of this patent

Making a defect free fin based device in lateral epitaxy overgrowth region

Life of this patent

Abstract

Claims18