High resistivity silicon-on-insulator substrate comprising an isolation region

A multilayer structure comprising:

• a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a bulk resistivity of at least about 500 Ohm-cm;
• an isolation region in interfacial contact with the front surface of the single crystal semiconductor handle substrate, wherein the isolation region comprising comprises an arsenic-doped semiconductor layer, has a thickness between about 50 angstroms and about 10,000 angstroms, and has a resistivity between about 1×1012 Ohm-cm and about 1×1014 ohm cm Ohm-cm;
• a semiconductor layer in interfacial contact with the isolation region, wherein the semiconductor layer comprises a polycrystalline semiconductor, an amorphous semiconductor, or a single crystal semiconductor, wherein the polycrystalline semiconductor, the amorphous semiconductor, or the single crystal semiconductor is selected from the group consisting of silicon (Si), silicon germanium (SiGe), silicon doped with carbon (SiC), and germanium (Ge), and the semiconductor layer has a thickness between about 50 nanometers and about 4000 nanometers;
• a dielectric layer in interfacial contact with the semiconductor layer;
• and
• a single crystal semiconductor device layer in interfacial contact with the dielectric layer.