Parallel test structure

A circuit for parallel testing of large numbers of devices on an integrated circuit chip, comprising:

• a voltage source;
• a current measuring device;
• devices under test connected to the voltage source;
• pass transistors connected between each device under test and the current measuring device;
• a decoder selectively providing a pass signal to each pass transistor, the decoder selecting a device for testing, wherein the decoder sequentially selects each device for testing by turning on each pass transistor to measure leakage current with the current measuring device;
• efuses, each of the efuses being connected to a different one of the devices under test between a device under test and a corresponding pass transistor, the efuses breaking an electric circuit for the device under test from the voltage source upon failure of a corresponding device under test;
• resistors, each of the resistors being connected to a different one of the efuses, the resistors providing a low resistance path to ground during stress conditions of a time-dependent dielectric breakdown (TDDB) test and forcing current to flow through the current measuring device when the pass transistors are turned on;
• and
• protection circuits connected between the efuses and ground, each protection circuit electrically isolating the decoder from the device under test upon failure of the device under test.

A method for parallel testing of large numbers of devices, the method comprising:

• providing an electrical circuit having devices for testing;
• providing a test voltage and applying the test voltage to the devices according to a time-dependent dielectric breakdown (TDDB) test on the devices;
• providing a decoder having a signal sequentially selecting each one of the devices undergoing the TDDB test;
• providing a current measuring device and individually measuring leakage current from the selected one of the devices;
• responsive to TDDB failure of any one of the devices, breaking an electric circuit for the one of the devices from the test voltage using efuses arranged in the electrical circuit;
• and
• responsive to TDDB failure of any one of the devices, electrically isolating the decoder from the one of the devices using protection circuits arranged in the electrical circuit.