Location-specific tuning of stress to control bow to control overlay in semiconductor processing
AssigneeTokyo Electron Limited
InventorAnton J. deVilliers
Life of this patent
Estimating the term…
Loading patent…
AssigneeTokyo Electron Limited
InventorAnton J. deVilliers
Estimating the term…
Techniques herein include systems and methods for correcting pattern overlay errors by correcting or adjusting bowing of wafers. Location-specific tuning of stress on semiconductor substrates reduces overlay error. Location-specific tuning of stress independently modifies specific regions, areas, or point locations on a substrate to change wafer bow at those specific locations, which reduces overlay error on substrates, which in turn improves overlay of subsequent patterns created on the substrate. Techniques herein include receiving a substrate with some amount of overlay error, measuring bow of the substrate to map z-height deviations across the substrate, generating an overlay correction pattern, and then physically modifying internal stresses on the substrate at specific locations with modifications independent of other coordinate locations. Such modifications can include etching a backside surface of the substrate. One or more processing modules can be used for such processing.
A system for correcting wafer overlay on a substrate having a front side working surface and a backside surface after a series of processing step on the front side working surface have occurred, the system comprising:
The system of claim I, wherein the metrology module configured to measure bow of the substrate comprises an optical sensor configured to measure bow of the substrate.
Dependencies are inferred from the claim text.