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US 10,475,524 B2Granted
Recovery of data read from memory with unknown polarity
AssigneeApple Inc.
InventorsAssaf Shappir, Eyal Gurgi
Life of this patent
Estimating the term…
Abstract
A memory controller includes an interface and circuitry. The interface is configured to communicate with a memory device, which includes multiple memory cells, and which applies refreshing to the memory cells by repeatedly inverting data stored in the memory cells. The circuitry is configured to store input data in a group of the memory cells, to read the stored input data from the group of the memory cells to produce read data, the read data has an actual polarity that is either un-inverted or inverted due to the refreshing of the memory cells in the group, to analyze the read data for identifying the actual polarity of the read data, and to recover the input data from the read data based on the identified actual polarity.
Claims20
A memory controller, comprising:
- an interface configured to communicate with a memory device comprising multiple memory cells, the memory device configured to refresh the memory cells by repeatedly inverting data stored in the memory cells;
- and
- circuitry configured to:
- encode input data into a Code Word (CW) using an Error Correction Code (ECC) that generates multiple parity bits, wherein both the CW and an inverted version of the CW in which a predefined group of one or more of the parity bits are inverted comprise valid code words of the ECC;
- store the CW in a group of the memory cells;
- read the stored CW from the group of the memory cells to produce read data, wherein due to the refresh of the memory cells in the group, the read data has an actual polarity that is either un-inverted or inverted;
- identify the actual polarity of the read data by decoding the ECC of the read data to produce decoded data;
- and
- recover the input data from the decoded data based on the identified actual polarity.
6 more elements
A method, comprising:
- encoding input data into a Code Word (CW) using an Error Correction Code (ECC) that generates multiple parity bits, wherein both the CW and an inverted version of the CW in which a predefined group of one or more of the parity bits are inverted comprise valid code words of the ECC;
- storing the CW in a group of memory cells of a memory device, which applies refreshing to the memory cells by repeatedly inverting the data stored in the memory cells;
- reading the stored CW from the group of the memory cells to produce read data, wherein due to the refreshing of the memory cells in the group, the read data has an actual polarity that is either un-inverted or inverted;
- identifying the actual polarity of the read data by decoding the ECC of the read data to produce decoded data;
- and
- recovering the input data from the decoded data based on the identified actual polarity.
3 more elements
A storage system, comprising:
- a memory comprising multiple memory cells, the memory is configured to refresh the memory cells by repeatedly inverting data stored in the memory cells;
- and
- a controller, which is configured to:
- encode input data into a Code Word (CW) using an Error Correction Code (ECC) that generates multiple parity bits, wherein both the CW and an inverted version of the CW in which a predefined group of one or more of the parity bits are inverted comprise valid code words of the ECC;
- store the CW in a group of the memory cells;
- read the stored CW from the group of the memory cells to produce read data, wherein due to the refresh of the memory cells in the group, the read data has an actual polarity that is either un-inverted or inverted;
- identify the actual polarity of the read data by decoding the ECC of the read data to produce decoded data;
- and
- recover the input data from the decoded data based on the identified actual polarity.
6 more elements
A memory controller, comprising:
- an interface configured to communicate with a memory device comprising multiple memory cells, the memory device configured to refresh the memory cells by repeatedly inverting data stored in the memory cells;
- and
- circuitry configured to:
- set a given bit of input data to a predefined value;
- encode the input data with the given bit set into a Code Word (CW) using an Error Correction Code (ECC) that generates multiple parity bits, such that encoding the input data and an inverted version of the input data results in same values of the multiple parity bits;
- store the CW in a group of the memory cells;
- read the stored CW from the group of the memory cells to produce read data, wherein due to the refresh of the memory cells in the group, the read data has an actual polarity that is either un-inverted or inverted;
- decode the ECC of the read data to produce decoded data;
- identify the actual polarity of the decoded data by checking the polarity of the given bit in the decoded data;
- and
- recover the input data from the decoded data based on the identified actual polarity.
8 more elements
Dependencies are inferred from the claim text.