Semiconductor storage device and test method thereof using a common bit line

A semiconductor storage device comprising:

• a plurality of first memory cells provided in a matrix manner in a first memory cell array;
• a plurality of first write word lines and a plurality of first read word lines, the first write word lines and the first read word lines being respectively provided in a plurality of rows of the plurality of first memory cells;
• a plurality of first write bit line pairs and a plurality of first read bit lines, the first write bit line pairs and the first read bit lines being respectively provided in a plurality of columns of the plurality of first memory cells;
• a first common bit line;
• a plurality of second memory cells provided in a matrix manner in a second memory cell array;
• a plurality of second write word lines and a plurality of second read word lines, the second write word lines and the second read word lines being respectively provided in a plurality of rows of the plurality of second memory cells;
• a plurality of second write bit line pairs and a plurality of second read bit lines, the second write bit line pairs and the second read bit lines being respectively provided in a plurality of columns of the plurality of second memory cells;
• a second common bit line;
• a first selection circuit that connects the first common bit line to one of the plurality of first read bit lines based on a control signal;
• a second selection circuit that connects the second common bit line to one of the plurality of second read bit lines based on the control signal;
• a first word line driver that activates any one of the plurality of first read word lines;
• a second word line driver that activates any one of the plurality of second read word lines;
• a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell;
• a sense amplifier that amplifies a potential difference between the first and second common bit lines;
• an output switching circuit that selectively outputs, as read data, one of an output signal of the sense amplifier and an inverted signal of the output signal, according to an attribute of a data read target memory cell,
• a test control circuit that activates, during a test mode, any of the write word lines corresponding to the data read target memory cell, and further activates either of the plurality of first read word lines or the plurality of second read word lines which are in the same row as the any of the write word lines, after a lapse of a predetermined period of time,
• wherein when the data read target memory cell belongs to the plurality of first memory cells, the output switching circuit outputs an output signal of the sense amplifier as the read data, and when the data read target memory cell belongs to the plurality of second memory cells, the output switching circuit outputs an inverted signal of the output signal of the sense amplifier as the read data, and
• wherein the output switching circuit includes:
• a first PMOS transistor having a source connected to a power supply voltage terminal, and a gate connected to the first common bit line;
• a second PMOS transistor having a source connected to a drain of the first PMOS transistor, a drain connected to an output terminal, and a gate supplied with a determination signal indicating whether or not a data read target memory cell belongs to the plurality of first memory cells;
• a first NMOS transistor having a source connected to a ground voltage terminal, and a gate connected to the first common bit line;
• a second NMOS transistor having a source connected to a drain of the first NMOS transistor, a drain connected to the output terminal, and a gate supplied with an inverted signal of the determination signal;
• a third PMOS transistor having a source connected to the power supply voltage terminal, and a gate connected to the second common bit line;
• a fourth PMOS transistor having a source connected to a drain of the third PMOS transistor, a drain connected to the output terminal, and a gate supplied with an inverted signal of the determination signal;
• a third NMOS transistor having a source connected to the ground voltage terminal, and a gate connected to the second common bit line;
• and
• a fourth NMOS transistor having a source connected to a drain of the third NMOS transistor, a drain connected to the output terminal, and a gate supplied with the determination signal.