Memory circuit including at least one marking cell and method of operating said memory circuit

A memory circuit, comprising:

• a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns;
• a plurality of word lines, each word line coupled with one or more memory cells of the plurality of memory cells;
• a plurality of electrically programmable non-volatile marking memory cells;
• wherein each word line is associated with one or more marking memory cells of the plurality of marking memory cells;
• wherein one or more marking memory cells in the marking memory cell array are in a known memory state, wherein the marking memory cells form a code configured to identify the associated word line of respective one or more marking memory cells in the known memory state, and
• wherein the memory circuit is configured to read, for each of the word lines, at least one memory cell of the one or more memory cells simultaneously with at least one marking memory cell of the one or more marking memory cells.

A method of operating a memory circuit comprising, the memory circuit comprising:

• a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns;
• a plurality of word lines, each word line coupled with one or more memory cells of the plurality of memory cells;
• a plurality of electrically programmable non-volatile marking memory cells;
• wherein at least one word line of the plurality of word lines is associated with one or more marking memory cells of the plurality of marking memory cells;
• and
• a plurality of marking bit lines, each marking bit line associated with one or more marking memory cells of the plurality of marking memory cells;
• a plurality of marking source lines, each marking source line associated with one or more marking memory cells of the plurality of marking memory cells;
• wherein, for one or more marking memory cells of the plurality of marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the one or more marking memory cells sets the one or more marking memory cells to a non-changeable memory state, wherein the plurality of marking memory cells is configured to identify the associated word line of respective one or more marking memory cells in the non-changeable memory state, and
• wherein the marking memory cells form a code configured to identify the associated word line of respective one or more marking memory cells in the non-changeable memory state, and
• wherein the physical connection from an associated marking source line and/or from an associated marking bit line to the one or more marking memory cells that sets the one or more marking memory cells to a non-changeable memory state is a disconnected physical connection from an associated marking source line and/or from an associated marking bit line to the one or more marking memory cells
• wherein the method comprises:
• reading one or more memory cells of the plurality of memory cells coupled to a word line of the plurality of word lines;
• and
• reading one or more of the marking memory cells associated with the word line.

A method of operating a memory circuit, the memory circuit comprising:

• a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns;
• a plurality of word lines, each word line coupled with one or more memory cells of the plurality of memory cells;
• a plurality of electrically programmable non-volatile marking memory cells;
• wherein each word line is associated with one or more marking memory cells of the plurality of marking memory cells;
• wherein one or more marking memory cells in the marking memory cell array are in a known memory state, wherein the marking memory cells form a code configured to identify the associated word line of respective one or more marking memory cells in the known memory state, and
• wherein the memory circuit is configured to read, for each of the word lines, at least one memory cell of the one or more memory cells simultaneously with at least one marking memory cell of the one or more marking memory cells,
• wherein the method comprises:
• reading at least one memory cell of the one or more memory cells coupled to a word line of the plurality of word lines simultaneously with at least one marking memory cell of the one or more marking memory cells associated with the word line.