Multi-decks memory device including inter-deck switches

An apparatus comprising

• first conductor materials located in different levels in a first portion of the apparatus, and first dielectric materials interleaved with the first conductor materials;
• second conductor materials located in different levels in a second portion of the apparatus, and second dielectric materials interleaved with the second conductor materials, each of the second conductor materials having a thickness in a direction perpendicular to the levels of the apparatus;
• third conductor materials located in different levels in third portion of the apparatus, and third dielectric materials interleaved with the third conductor materials, the second portion of the apparatus being between the first and third portions of the apparatus;
• an opening in each of the second conductor materials;
• and
• a polysilicon plug in the opening, the polysilicon plug being separated from each of the second conductor materials by a dielectric structure, the polysilicon plug having a thickness in the direction perpendicular to the levels of the apparatus, wherein the thickness of the polysilicon plug is greater than the thickness of each of the second conductor materials.

An apparatus comprising:

• a first deck of first memory cells located in different levels in a first portion of the apparatus;
• a second deck of second memory cells located in different levels in a second portion of the apparatus;
• a third deck of third memory cells located in different levels in a third portion of the apparatus;
• a first interface between the first and second decks, the first interface including a first switch and a first control gate to control the first switch;
• second interface between the second and third decks, the second interface including a second switch and a second control gate to control the second switch;
• and a channel extending through the first deck, the second deck, at least a portion of the third deck, the first interface, and the second interface, the channel being separated from charge storage portions of the first, second, and third memory cells by a dielectric structure, the dielectric structure including a first thickness, wherein the first and second interfaces include:
• a first additional dielectric structure between the channel and a sidewall of the first control gate, the first additional dielectric structure including a second thickness in a direction from the channel to the sidewall of the first control gate;
• and a second additional dielectric structure between the channel and a sidewall the second control gate, the second additional dielectric structure including a third thickness in a direction from the channel to the sidewall of the second control gate, wherein at least one of the second and third thicknesses is greater than the first thickness.