Resistive memory and resistance window recovery method of resistive memory cell thereof

A resistive memory, comprising:

• a resistive memory cell;
• a word line signal providing circuit coupled to a word line of the resistive memory cell;
• a bit line signal providing circuit coupled to a bit line of the resistive memory cell;
• and
• a source line signal providing circuit coupled to a source line of the resistive memory cell, wherein when a resistance window recovery method is performed, the bit line signal providing circuit and the source line signal providing circuit apply an over reset voltage difference between a top electrode and a bottom electrode of the resistive memory cell during a first period, the bit line signal providing circuit and the source line signal providing circuit apply a set voltage difference between the top electrode and the bottom electrode of the resistive memory cell during a second period to increase a compliance current of the resistive memory cell, and the word line signal providing circuit, the bit line signal providing circuit and the source line signal providing circuit perform a first reset operation by applying a reset voltage difference between the top electrode and the bottom electrode of the resistive memory cell during a third period, wherein the over reset voltage difference falls in a reset complementary switching voltage range of the resistive memory cell,
• wherein the over reset voltage difference is larger than the reset voltage difference.