Single-ended reading circuit
AssigneeShanghai Zhaoxin Semiconductor Co., Ltd.
InventorLiang Man
Life of this patent
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Abstract
A single-ended reading circuit includes a pre-charger, a high-level maintainer, a first NAND gate, a second NAND gate, a third NAND gate, and an output driver. The first NAND gate has a first input terminal for receiving a pre-charging clock, a second input terminal coupled to a first node, and an output terminal coupled to a second node. The second NAND gate has a first input terminal coupled through a third node to the second node, a second input terminal coupled to a fourth node, and an output terminal coupled to a fifth node. The third NAND gate has a first input terminal coupled to the fifth node, a second input terminal coupled to the first node, and an output terminal coupled to the fourth node.
Claims13
A single-ended reading circuit, comprising:
- a pre-charger, coupled to a bit-line node;
- a high-level maintainer, coupled to the bit-line node, wherein the pre-charger and the high-level maintainer are configured to selectively pull up a bit-line voltage at the bit-line node;
- a first NAND gate, wherein the first NAND gate has a first input terminal for receiving a pre-charging clock, a second input terminal coupled to a first node, and an output terminal coupled to a second node, wherein the first node is directly electrically connected to the bit-line node;
- a second NAND gate, wherein the second NAND gate has a first input terminal coupled to the second node, a second input terminal coupled to a fourth node, and an output terminal coupled to a fifth node;
- a third NAND gate, wherein the third NAND gate has a first input terminal coupled to the fifth node, a second input terminal coupled to the first node, and an output terminal coupled to the fourth node;
- and
- an output driver, coupled to the fourth node, and generating an output voltage at an output node.
Dependencies are inferred from the claim text.