Low power delay buffer between equalizer and high sensitivity slicer
AssigneeIntegrated Device Technology, Inc.
InventorDavid Chang
Life of this patent
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Abstract
An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate signal may be differential. The slicer may be configured to generate an output signal by slicing the second intermediate signal. The output signal may be single-ended.
Claims18
An apparatus comprising:
- a continuous-time linear equalizer circuit configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage, wherein (i) said input signal is single-ended and (ii) said first intermediate signal is differential;
- a buffer configured to generate a second intermediate signal by delaying said first intermediate signal, wherein said second intermediate signal is differential;
- and
- at least one slicer configured to generate an output signal by slicing said second intermediate signal, wherein said output signal is single-ended.
A method for delay between an equalizer and at least one slicer, comprising the steps of:
- generating a first intermediate signal by equalizing an input signal relative to a reference voltage with a continuous-time linear equalizer, wherein (i) said input signal is single-ended and (ii) said first intermediate signal is differential;
- generating a second intermediate signal by delaying said first intermediate signal with a buffer, wherein said second intermediate signal is differential;
- and
- generating an output signal by slicing said second intermediate signal with said slicer, wherein said output signal is single-ended.
Dependencies are inferred from the claim text.