Back to results
US 10,475,497 B2Granted
Self-referenced sense amplifier with precharge
AssigneeEverspin Technologies, Inc.
InventorsSyed M. Alam, Chitra Subramanian
Life of this patent
Estimating the term…
Abstract
Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.
Claims18
A method of operation of a memory cell that includes a magnetic tunnel junction having a first end and a second end, comprising:
- applying a read voltage across the magnetic tunnel junction using a first circuit coupled between a first node and a first line, wherein the first line is coupled to the first end of the magnetic tunnel junction;
- while applying the read voltage, sampling a sample voltage on the first node, wherein the sample voltage results from current flow through the magnetic tunnel junction based on the read voltage on the first line;
- after sampling the sample voltage, applying a first write current through the magnetic tunnel junction to place the magnetic tunnel junction in a known first state;
- after applying the first write current:
- precharging the first line to a low voltage;
- after precharging the first line to the low voltage, re-applying the read voltage across the magnetic tunnel junction;
- and
- comparing the sample voltage with an evaluation voltage on the first node to determine an initial state of the magnetic tunnel junction, wherein the evaluation voltage results from re-applying the read voltage;
- and
- after determining the initial state of the magnetic tunnel junction, storing a second state in the magnetic tunnel junction, wherein storing the second state in the magnetic tunnel junction includes:
- precharging a second line to a second high voltage, wherein the second line is coupled to the second end of the magnetic tunnel junction;
- and
- applying a second write current through the magnetic tunnel junction, wherein the first write current flows through the magnetic tunnel junction before flowing through a corresponding selection transistor of the memory cell, and wherein the second write current flows through the corresponding selection transistor before the magnetic tunnel junction.
10 more elements
An apparatus comprising:
- a memory cell that includes a magnetic tunnel junction coupled in series with a selection transistor;
- preamplifier circuitry coupled to a first end of the memory cell by a first line, wherein the preamplifier circuitry includes a capacitor;
- a first NMOS-follower circuit coupled to the first line;
- a first PMOS-follower circuit coupled to a second end of the memory cell by a second line;
- a first precharge transistor coupled between the first line and a first low voltage source;
- a second precharge transistor coupled to the second line;
- and
- control circuitry coupled to the preamplifier circuitry, the first NMOS-follower circuit, the first PMOS-follower circuit, a gate of the first precharge transistor, and a gate of the second precharge transistor, the control circuitry configured to:
- apply a read voltage across the magnetic tunnel junction during a first sense phase using the preamplifier circuitry, wherein a sample voltage corresponding to current through the magnetic tunnel junction as a result of the read voltage is stored in the capacitor during the first sense phase;
- after the first sense phase, apply a first write current through the magnetic tunnel junction using the first NMOS-follower circuit, wherein the first write current places the magnetic tunnel junction in a known first state;
- after applying the first write current, apply a voltage pulse to the gate of the first precharge transistor such that the first precharge transistor pulls the first line to a low voltage after the magnetic tunnel junction is placed in the known first state;
- and
- apply a precharge control voltage to the second precharge transistor prior to a write-back operation in which a second write current is generated through the magnetic tunnel junction, wherein the second precharge transistor pulls the second line to a high voltage prior to initiation of the second write current.
10 more elements
An apparatus comprising:
- a memory cell that includes a magnetic tunnel junction coupled in series with a selection transistor;
- a first NMOS-follower circuit coupled between a first node and a first end of the memory cell;
- a second NMOS-follower circuit coupled to the first end of the memory cell;
- a first precharge transistor coupled between the first end of the memory cell and a first low voltage source;
- a second precharge transistor coupled to a second end of the memory cell;
- and
- control circuitry coupled to the first NMOS-follower circuit, the second NMOS follower circuit, a gate of the first precharge transistor, and a gate of the second precharge transistor, the control circuitry configured to:
- apply a read voltage across the magnetic tunnel junction during a first sense phase using the first NMOS-follower circuit, wherein a sample voltage corresponding to current through the magnetic tunnel junction as a result of the read voltage is stored during the first sense phase;
- after the first sense phase, apply a first write current through the magnetic tunnel junction using the second NMOS-follower circuit, wherein the first write current places the magnetic tunnel junction in a known first state;
- after the magnetic tunnel junction is placed in the known first state, pull the first end of the memory cell to a low voltage using the first precharge transistor;
- after pulling the first end of the memory cell to the low voltage, re-apply the read voltage across the magnetic tunnel junction during a second sense phase using the first NMOS-follower circuit;
- and
- apply a precharge control voltage to the second precharge transistor prior to a write-back operation in which a second write current is generated through the magnetic tunnel junction, wherein the second precharge transistor pulls the second line to a high voltage prior to initiation of the second write current.
10 more elements
Dependencies are inferred from the claim text.