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US 10,475,494 B2Granted
Memory device and memory system including the same
AssigneeSK hynix Inc.
InventorsWoongrae Kim, Tae-Yong Lee
Life of this patent
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Abstract
A semiconductor device may include: a holding control circuit suitable for generating a holding control signal and an option setting information signal, based on a first command signal; a holding circuit suitable for generating a held option setting information signal based on the holding control signal and the option setting information signal; an operation control circuit suitable for generating an operation mode signal based on a second command signal; a setting control circuit suitable for generating a setting control signal based on the operation mode signal and the held operation setting information signal; and a memory region suitable for performing an operation based on the setting control signal and the operation mode signal.
Claims19
A memory device comprising:
- a holding control circuit suitable for generating a holding control signal and an option setting information signal, based on a first command signal;
- a holding circuit suitable for generating a held option setting information signal based on the holding control signal and the option setting information signal;
- an operation control circuit suitable for generating an operation mode signal based on a second command signal;
- a setting control circuit suitable for generating a setting control signal based on the operation mode signal and the held operation setting information signal;
- and
- a memory region suitable for performing an operation based on the setting control signal and the operation mode signal.
3 more elements
A memory device comprising:
- a holding control circuit suitable for generating a holding control signal and an option setting information signal based on a first command signal, during a holding period;
- a holding circuit suitable for generating a held option setting information signal based on the holding control signal and the option setting information signal during the holding period, and retaining the held option setting information signal during an operation period following the holding period;
- an operation control circuit suitable for generating an operation mode signal and an address signal based on a second command signal, during the operation period;
- a setting control circuit suitable for generating a setting control signal based on the held option setting information signal and the operation mode signal, during the operation period;
- and
- a memory region suitable for performing a write operation or read operation based on the setting control signal, the operation mode signal and the address signal.
3 more elements
A memory device comprising:
- a holding control circuit suitable for generating a synchronized holding control signal and an option setting information signal based on a first command signal including one or more first code signals and one or more second code signals, during a holding period;
- a holding circuit suitable for generating a held option setting information signal based on the synchronized holding control signal and the option setting information signal during the holding period, and retaining the held option setting information signal during an operation period following the holding period;
- an operation control circuit suitable for generating an operation mode signal and an address signal based on a second command signal, during the operation period;
- a setting control circuit suitable for generating a setting control signal based on the held operation setting information signal and the operation mode signal, during the operation period;
- and
- a memory region suitable for performing a write operation or read operation based on the setting control signal, the operation mode signal and the address signal,
- wherein the holding control circuit comprises:
- a first decoding unit suitable for generating the holding control signal based on the first code signal;
- a synchronization unit suitable for generating a synchronized holding control signal by synchronizing the holding control signal with a control clock signal;
- and
- a second decoding unit suitable for generating the option setting information signal based on the synchronized holding control signal and the second code signal, and
- the holding circuit comprises an asynchronous latch.
9 more elements
A memory system comprising:
- a control device suitable for generating a first command signal corresponding to first option setting information during a first holding period, and generating a second command signal corresponding to a first operation mode during a first operation period;
- and
- a memory device suitable for holding the first command signal, and performing an operation according to the first option setting information and the first operation mode based on the second command signal and the held first command signal.
An operating method for a memory system comprising:
- generating, by a control device, a first command signal corresponding to first option setting information during a first holding period, and generating a second command signal corresponding to a first operation mode during a first operation period;
- and
- holding the first command signal and performing an operation, by a memory device, according to the first option setting information and the first operation mode based on the second command signal and the held first command signal.
Dependencies are inferred from the claim text.