Word-line pre-charging in power-on read operation to reduce programming voltage leakage
AssigneeSanDisk Technologies LLC
InventorsManabu Sakai, Qui Vi Nguyen, Yen-Lung Li
Life of this patent
Estimating the term…
Abstract
This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.
Claims21
An apparatus comprising:
- a plurality of memory cells;
- a plurality of word lines connected to the plurality of memory cells;
- a global control line;
- and
- a low-voltage generator configured to:
- apply a low-voltage pulse to at least one of the plurality of word lines during a time period prior to a first memory operation of at least one of the plurality of memory cells occurring after power is applied to the plurality of memory cells to pre-charge the at least one word line;
- and
- apply a voltage having the same magnitude as the low-voltage pulse to the global control line after a conclusion of the low-voltage pulse.
A system comprising:
- a plurality of memory cells;
- a plurality of word lines connected to the plurality of memory cells;
- a row decoder;
- and
- a low-voltage generator configured to:
- apply a low-voltage pulse to all of the plurality of word lines of at least one of the plurality of memory cells to pre-charge the plurality of word lines during a time in which the row decoder is idle;
- and
- apply a word line setup signal having a magnitude greater than that of the low-voltage pulse to activate each of the plurality of memory blocks during a word line setup phase, prior to the low-voltage generator applying the low-voltage pulse.
A method for reducing leakage in a non-volatile memory, the method comprising:
- applying, by a low-voltage generator during an idle period of a row decoder, a low-voltage pulse to a plurality of word-lines of the non-volatile memory;
- applying a voltage having the same magnitude as the low-voltage pulse to a global control line after the end of the idle period of the row decoder;
- and
- performing a memory operation on a memory cell of the non-volatile memory via at least one of the plurality of word-lines.
An apparatus comprising:
- a plurality of memory cells;
- a plurality of word lines connected to the plurality of memory cells;
- means for applying a low-voltage pulse to at least one of the plurality of word lines during a power-on read operation of at least one of the plurality of memory cells to pre-charge the at least one word line;
- and
- means for applying a voltage having the same magnitude as the low-voltage pulse to a global control line after a conclusion of the low-voltage pulse.
Dependencies are inferred from the claim text.