Circuit and method for read latency control
AssigneeMacronix International Co., Ltd.
InventorsShang-Chi Yang, Chun-Yu Liao, Yi-Wei Chang
Life of this patent
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Abstract
A memory device comprises an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells. A controller is configured to execute a read operation in response to a command and address, including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers, and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal.
Claims29
A memory device, comprising:
- an array of memory cells;
- a plurality of sense amplifiers coupled with the memory cells;
- a controller configured to execute a read operation in response to a command and address, including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers, and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal;
- and
- circuitry to generate the timing signal including a first delay circuit generating a first signal having a first delay based on a frequency of a read clock signal, a second delay circuit generating a second signal having a second delay independent of the frequency of the read clock signal, and a selector circuit to generate the timing signal in response to the first signal if the first delay is shorter than the second delay, or in response to the second signal if the second delay is shorter than the first delay.
A method for reading a memory device, the memory device comprising an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells, the method comprising:
- receiving an address synchronized with a read clock signal;
- electrically coupling the memory cells at the address to the sense amplifiers in a read cycle;
- electrically decoupling the memory cells at the address from the sense amplifiers in the read cycle in response to a timing signal;
- and
- generating the timing signal including:
- generating a first signal having a first delay based on a frequency of the read clock signal;
- generating a second signal having a second delay independent of the frequency of the read clock signal;
- and
- generating the timing signal in response to the first signal if the first delay is shorter than the second delay, or in response to the second signal if the second delay is shorter than the first delay.
A circuit, comprising:
- a first delay circuit generating a first signal having a first delay based on a frequency of a read clock signal;
- a second delay circuit generating a second signal having a second delay independent of the frequency of the read clock signal;
- and
- a selector circuit to generate a timing signal in response to the first signal if the first delay is shorter than the second delay, or in response to the second signal if the second delay is shorter than the first delay.
A memory device, comprising:
- an array of memory cells;
- a plurality of sense amplifiers coupled with the memory cells;
- a controller configured to execute a read operation in response to a command and address;
- and
- circuitry to generate a timing signal including a first delay circuit generating a first signal having a first delay based on a frequency of a read clock signal, a second delay circuit generating a second signal having a second delay independent of the frequency of the read clock signal, and a selector circuit to generate the timing signal in response to the first signal if the first delay is shorter than the second delay, or in response to the second signal if the second delay is shorter than the first delay.
A method for reading a memory device, the memory device comprising an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells, the method comprising:
- receiving an address synchronized with a read clock signal;
- and
- generating a timing signal including:
- generating a first signal having a first delay based on a frequency of the read clock signal;
- generating a second signal having a second delay independent of the frequency of the read clock signal;
- and
- generating the timing signal in response to the first signal if the first delay is shorter than the second delay, or in response to the second signal if the second delay is shorter than the first delay.
Dependencies are inferred from the claim text.