Random code generator with antifuse differential cell and associated sensing method

A random code generator, comprising:

• a memory cell array comprising plural antifuse differential cells;
• and
• a sensing circuit having an input terminal and an inverted input terminal, wherein when a first antifuse differential cell of the memory cell array is a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit,
• wherein the sensing circuit further comprises a first current sink capable of generating a first bias current and a second current sink capable of generating a second bias current;
• wherein the first current sink comprises a first transistor and a second transistor;
• a drain terminal of the first transistor is connected with the input terminal of the sensing circuit;
• a gate terminal of the first transistor receives a first bias voltage;
• a drain terminal of the second transistor is connected with a source terminal of the first transistor;
• a gate terminal of the second transistor receives a read enabling signal;
• and a source terminal of the second transistor is connected with the ground terminal;
• wherein the second current sink comprises a third transistor and a fourth transistor;
• a drain terminal of the third transistor is connected with the inverted input terminal of the sensing circuit;
• a gate terminal of the third transistor receives a second bias voltage;
• a drain terminal of the fourth transistor is connected with a source terminal of the third transistor;
• a gate terminal of the fourth transistor receives the read enabling signal;
• and a source terminal of the fourth transistor is connected with the ground terminal;
• wherein during a read cycle, the selected cell generates a first read current and a second read current;
• a first charging current is generated by subtracting the first bias current from the first read current to charge the bit line;
• and a second charging current is generated by subtracting the second bias current from the second read current to charge the inverted bit line,
• wherein if a first voltage of the bit line is higher than a second voltage of the inverted bit line, the sensing circuit discharges the second voltage of the inverted bit line to enhance a voltage difference between the bit line and the inverted bit line, wherein if the second voltage of the inverted bit line is higher than the first voltage of the bit line, the sensing circuit discharges the first voltage of the bit line to enhance the voltage difference between the bit line and the inverted bit line, wherein the sensing circuit judges a storage state of the selected cell according to the voltage difference and determines a bit of a random code according to the storage state of the selected cell.