Data driver and display apparatus having the same
AssigneeSamsung Display Co., Ltd.
InventorsGuhui Jo, Wontae Kim, Sun-koo Kang, Taegon Im
Life of this patent
Estimating the term…
Abstract
A data driver includes a first latch, a second latch, a digital-to-analog converter, and an output buffer. The first latch sequentially stores first line data in response to a first sampling signal and outputs the stored data in parallel. The second latch sequentially stores second line data in response to a second sampling signal and outputs the stored data in parallel. The digital-to-analog converter converts the parallel data provided from one of the first and second latches to data voltages. The output buffer outputs the data voltages in response to a delay clock.
Claims20
A data driver comprising:
- a first latch which sequentially stores first line data in response to a first sampling signal and outputs the stored data in parallel;
- a second latch which sequentially stores second line data in response to a second sampling signal and outputs the stored data in parallel;
- a digital-to-analog converter which converts the parallel data provided from one of the first and second latches to data voltages;
- and
- an output buffer which outputs the data voltages in response to a delay clock.
A display apparatus comprising:
- a display panel which comprises a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines to display an image;
- a gate driver which generates a plurality of gate signals and applies the gate signals to the gate lines;
- a plurality of data drivers which generates a plurality of data voltages based on output image data and applies the data voltages to the data lines;
- and
- a signal controller which controls an operation of the gate driver and the data drivers and generates the output image data based on input image data,
- wherein each of the data drivers comprises first to n-th channels connected to corresponding data lines among the data lines, and each of the data drivers generates first to n-th delay clock signals in which delay information is reflected respectively and which correspond to the first to n-th channels and provides the first and n-th delay clock signals of the first to n-th delay clock signals to a next data driver in order among the data drivers.
A display apparatus comprising:
- a display panel which comprises a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines to display an image;
- a gate driver which generates a plurality of gate signals and applies the gate signals to the gate lines;
- a plurality of data drivers which generates a plurality of data voltages based on output image data and applies the data voltages to the data lines;
- and
- a signal controller which controls an operation of the gate driver and the data drivers and generates the output image data based on input image data,
- wherein each of the data drivers comprises:
- first to n-th channels connected to corresponding data lines among the data lines;
- a first latch which sequentially stores first line data in response to a first sampling signal and outputs the stored data in parallel;
- a second latch which sequentially stores second line data in response to a second sampling signal and outputs the stored data in parallel;
- a digital-to-analog converter which converts the parallel data provided from one of the first and second latches to data voltages;
- and
- an output buffer which outputs the data voltages in response to a delay clock.
Dependencies are inferred from the claim text.