Gate drive circuit, display panel, and driving method for the gate drive circuit

A display panel, comprising a gate drive circuit, the gate drive circuit comprises a plurality of shift register units connected in cascade, wherein an output end of a shift register unit at level n is connected to an input end of a shift register unit at level n+x;

• a reset end of the shift register unit at level n is connected to an output end of the shift register unit at level n+x, wherein x is an integer greater than 1, n is an arbitrary integer greater than 0 and less than or equal to N−x, and N represents a total number of shift register units comprised in the gate drive circuit;
• wherein the gate drive circuit further comprises buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels, wherein:
• a buffer unit at level m is connected to an output end of a shift register unit at level m and an output end of a shift register unit at level m+1+x, and configured to start outputting an effective pulse signal when the output end of the shift register unit at level m outputs an effective pulse signal, and to stop outputting the effective pulse signal output by the buffer unit at level m when the output end of the shift register unit at level m+1+x outputs an effective pulse signal, wherein m is an arbitrary odd number between 1 and N−1−x;
• a buffer unit at level k is connected to an output end of a shift register unit at level k, an output end of a shift register unit at level k+1+x and a touch control switch unit corresponding to the shift register unit at level k, and configured to output an effective pulse signal under control of the touch control switch unit corresponding to the shift register unit at level k only when the output end of the shift register unit at level k outputs an effective pulse signal, or configured to start outputting an effective pulse signal when the output end of the shift register unit at level k outputs an effective pulse signal, and to stop outputting the effective pulse signal output by the buffer unit at level k when the output end of the shift register unit at level k+1+x outputs an effective pulse signal, wherein k is an arbitrary even number between 1 and N−1−x.