Fan-out semiconductor package

A fan-out semiconductor package comprising:

• first insulating layers having a through-hole penetrating through outermost surfaces of the first insulating layers opposing each other;
• first redistribution layers alternately disposed separated by the first insulating layers;
• first vias disposed in the first insulating layers, respectively, and electrically connecting the first redistribution layers to each other;
• a semiconductor chip disposed in the through-hole of the first insulating layers, and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface;
• an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip;
• second insulating layers and second redistribution layers alternately disposed on one side of the semiconductor chip, the first insulating layers, and the first redistribution layers;
• and
• second vias disposed in the second insulating layers, respectively, and electrically connecting the second redistribution layers to each other,
• wherein the second redistribution layers are electrically connected to the connection pads,
• one of the second redistribution layers includes sensor patterns recognizing a fingerprint and protrudes from one of the second insulating layers, and another of second redistribution layers includes an electromagnetic wave blocking pattern disposed between the semiconductor chip and the sensor patterns, and
• the one of the second insulating layers, from which the one of the second redistribution layers including the sensor patterns protrudes, is disposed between the semiconductor chip and the one of the second redistribution layers including the sensor patterns.

A fan-out semiconductor package comprising:

• a first insulating layer having a through-hole;
• a semiconductor chip disposed in the through-hole of the first insulating layer, and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface;
• an encapsulant covering one of the inactive surface and the active surface of the semiconductor chip, covering one of major surfaces of the first insulating layer, and extending continuously from the covered surface of the semiconductor chip and the covered major surface of the first insulating layer to fill at least a portion of the through-hole;
• a first upper redistribution layer, a first upper insulating layer, a second upper redistribution layer, and a second upper insulating layer sequentially disposed on the semiconductor chip and the first insulating layer;
• a lower redistribution layer disposed between the second upper insulating layer and the semiconductor chip;
• and
• a lower insulating layer, from which the lower redistribution layer protrudes, disposed between the lower redistribution layer and the semiconductor chip,
• wherein the first and second upper redistribution layers and the lower redistribution layer are electrically connected to the connection pads,
• the first and second upper redistribution layers each include sensor patterns recognizing a fingerprint, and protrude from the first and second upper insulating layers, respectively, and
• the lower insulating layer is in physical contact with the semiconductor chip.