Simultaneous multi-processor (SiMulPro) apparatus, simultaneous transmit and receive (STAR) apparatus, DRAM interface apparatus, and associated methods

An apparatus including:

• UB) a core, a core module, a Programmable Execution Module (PEM), an ASIC, a chip, a Memory Access Processor (MAP), a Memory Access processor Module (MAM), a DRAM Data Unit (DDU) and/or a Task Control DRAM Unit (TCDU) collectively referred to as a claimed apparatus component including
• UB1) a task controller communicatively coupled to a task network and adapted to respond to at least one received task message to generate a Task Wave Front (TWF) issued to at least one instruction pipe, each instruction pipe containing at least one instructed resource further containing a task resource for each of at least two tasks, referred to as task 0 and task 1;
• UB2) wherein said TWF includes a task command which can halt, run, or set which of said tasks is active, wherein no more than one of said tasks can be active at one time;
• and
• UB3) a Simultaneous Multi-Processor (SiMulPro) core implementing a V2LIW instruction processing of a plurality of said instructed resources performing at least two simultaneous processes, referred to as V2LIW instructed resources, and replacing a superscalar interpreter, an instruction cache, and a multi-thread controller in hardware by configurable control of said hardware by software in said claimed apparatus component;
• and
• UC) wherein a communication network consists essentially of said task network and a data network, wherein said task network is communicatively separated from said data network,
• UC1) wherein a data message traversing said data network cannot alter a second task related message traversing said task network, and
• UC2) wherein said second task related message cannot alter said data message.