Secure memory implementation for secure execution of Virtual Machines

A non-transitory computer program product comprising:

• a data processing circuit to process data in a first mode and a second mode, and to send commands to a chip interconnect bus using real addresses;
• wherein the chip interconnect bus transports a number of bits for the real addresses;
• wherein the chip interconnect bus is larger than a number of bits needed for a maximum memory range supported by the computer system;
• wherein a first portion of the bits for real addresses which are not in the range of the supported maximum memory range is used to indicate whether to operate in the first mode or the second mode creating a memory address hole;
• a memory controller operatively coupled to a memory component;
• one or more computer readable storage media;
• program instructions stored on the one or more computer readable storage media for execution by one or more computer processors, the program instructions comprising:
• program instructions to specify a secure memory range by using range registers;
• program instructions to, responsive to determining that the real address is detected to be in the secure memory range to match a memory component address, set a real address bit;
• program instructions to, responsive to determining that the real address is in the memory address hole, detect a security access violation;
• and
• program instructions to, responsive to determining that the real address is not in the secure address range and the real address bit is set, detect the security access violation.