Layout placement mapping from schematic placement of circuit cells
AssigneeCadence Design Systems, Inc.
InventorKuoching Lin
Life of this patent
Estimating the term…
Abstract
The present embodiments relate to implementing an integrated circuit design where a layout of circuit cells on a semiconductor chip is based on positions of the circuit cells on a schematic. According to some aspects, embodiments relate to a method for identifying a plurality of sub-regions on a semiconductor chip layout where each sub-region has a placement constraint. The method further includes assigning circuit cells to sub-regions based on the constraints. The method also includes clustering the circuit cells into clusters based on their positions on the schematic. Circuit cells from each cluster are placed in one or more of the sub-regions based on the proximity of the centers of the clusters to the centers of the sub-regions.
Claims20
A method for implementing a design for an integrated circuit, comprising:
- providing a schematic of a circuit having a plurality of circuit cells, each of the plurality of circuit cells having a cell-type;
- identifying a plurality of sub-regions on a semiconductor chip, each sub-region having an associated constraint that restricts placement of circuit cells within its boundaries to one or more cell-types based at least on physical or electrical properties of the circuit cells;
- assigning a first subset of circuit cells, from the plurality of circuit cells, to a first subset of the sub-regions according to the constraint associated with each sub-region in the first subset of the sub-regions;
- clustering the first subset of circuit cells based on their positions on the schematic into m1 clusters of circuit cells, wherein m1 denotes a number of sub-regions in the first subset of the sub-regions;
- and
- causing each of the m1 clusters of circuit cells to be located within one or more sub-regions of the first subset of the sub-regions, according to proximity of a center of each of the m1 clusters to centers of sub-regions of the first subset of the sub-regions.
A non-transitory computer readable storage medium having instructions stored thereon which, when executed by a computer, cause the computer to execute a method for implementing a design for an integrated circuit, the method comprising:
- providing a schematic of a circuit having a plurality of circuit cells, each of the plurality of circuit cells having a cell-type;
- identifying a plurality of sub-regions on a semiconductor chip, each sub-region having an associated constraint that restricts placement of circuit cells within its boundaries to one or more cell-types based at least on physical or electrical properties of the circuit cells;
- assigning a first subset of circuit cells, from the plurality of circuit cells, to a first subset of the sub-regions according to the constraint associated with each sub-region in the first subset of the sub-regions;
- clustering the first subset of circuit cells based on their positions on the schematic into m1 clusters of circuit cells, wherein m1 denotes a number of sub-regions in the first subset of the sub-regions;
- and
- causing each of the m1 clusters of circuit cells to be located within one or more sub-regions of the first subset of the sub-regions, according to proximity of a center of each of the m1 clusters to centers of sub-regions of the first subset of the sub-regions.
A system for implementing a design of an integrated circuit, comprising one or more processors, the one or more processors configured to:
- provide a schematic of a circuit having a plurality of circuit cells, each of the plurality of circuit cells having a cell-type;
- identify a plurality of sub-regions on a semiconductor chip, each sub-region having an associated constraint that restricts placement of circuit cells within its boundaries to one or more cell-types based at least on physical or electrical properties of the circuit cells;
- assign a first subset of circuit cells, from the plurality of circuit cells, to a first subset of the sub-regions according to the constraint associated with each sub-region in the first subset of the sub-regions;
- cluster the first subset of circuit cells based on their positions on the schematic into m1 clusters of circuit cells, wherein m1 denotes a number of sub-regions in the first subset of the sub-regions;
- and
- cause each of the m1 clusters of circuit cells to be located within one or more sub-regions of the first subset of the sub-regions, according to proximity of a center of each of the m1 clusters to centers of sub-regions of the first subset of the sub-regions.
Dependencies are inferred from the claim text.