Virtual hierarchical layer usage

A computer system for generating a layout of a semiconductor integrated circuit, the computer system comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors are configured to:
• identify a cell design within a semiconductor design layout that includes a plurality of layers and a plurality of hierarchical levels;
• determine an instance of the cell design and shapes which traverse the instance;
• generate a virtual layer corresponding to one of the plurality of layers within the semiconductor design layout which includes one or more of the shapes which traverse the instance;
• augment the virtual layer with information on other shapes which traverse other instances of the cell design within the semiconductor design layout;
• and
• accumulate overlapping shape data of shapes overlapping a region adjacent to the instance.

A computer program product embodied in a non-transitory computer readable medium, which when executed by a processor, causes the processor to generate a layout of a semiconductor integrated circuit, the computer program product comprising instructions that when executed cause the processor to:

• identify a cell design within a semiconductor design layout that includes a plurality of layers and a plurality of hierarchical levels;
• determine an instance of the cell design and shapes which traverse the instance;
• generate a virtual layer corresponding to one of the plurality of layers within the semiconductor design layout which includes one or more of the shapes which traverse the instance;
• augment the virtual layer with information on other shapes which traverse other instances of the cell design within the semiconductor design layout;
• and
• accumulate overlapping shape data of shapes overlapping a region adjacent to the instance.