Power and performance sorting of microprocessors from first interconnect layer to wafer final test

A computer-implemented system for manufacturing integrated circuits ICs comprising:

• a memory storage device;
• a processor unit coupled to said memory storage device and configured to:
• conduct in-line parametric measurements of performance-predictive parameters after a deposition of a first metallization level of an IC chip being manufactured, said performance-predictive parameters data including a quiescent current (IDDQ) leakage power and a performance scaling ring oscillator (PSRO) delay of a PSRO test structure;
• input said IDDQ leakage power and PSRO delay performance-predictive parameters measurements data into a stored performance classifying model;
• run said stored performance classifying model for determining a final frequency and power performance of said IC chip being manufactured based on said input IDDQ leakage power and PSRO delay performance-predictive parameters measurements, said performance classifying model built using an adaptive learning algorithm and a training data set, the training data set comprising:
• obtained first metallization level performance-predictive parameter measurements data obtained from each of plural prior-tested IC chip samples during their manufacture and final performance metrics data associated with each said plural prior-tested IC sample after its manufacture, and said model using a complex power sorting criterion for IC performance classification, said complex power sorting criterion defining a non-linear power sort threshold as a combined function of both the quiescent current (IDDQ) leakage power and the performance scaling ring oscillator (PSRO) delay in-line parametric measurements, the threshold defining a non-linear region for determining said final frequency and power product performance for said IC chip being manufactured;
• and
• in response to said determining, modify a manufacturing step to optimize a manufacturing process to achieve a defined product performance specification for the IC chip being manufactured.

A computer program product comprising a non-transitory computer useable medium, said medium readable by a processing circuit and storing instructions run by a processing circuit for performing a method of manufacturing integrated circuits ICs, the method comprising:

• conducting in-line parametric measurements of performance-predictive parameters after a deposition of a first metallization level of an IC chip being manufactured, said performance-predictive parameters data including a quiescent current (IDDQ) leakage power and a performance scaling ring oscillator (PSRO) delay of a PSRO test structure;
• inputting said IDDQ leakage power and PSRO delay performance-predictive parameters measurements data into a stored performance classifying model;
• running said stored performance classifying model for determining a final frequency and power performance of said IC chip being manufactured based on said input IDDQ leakage power and PSRO delay performance-predictive parameters measurements, said performance classifying model built using an adaptive learning algorithm and a training data set, the training data set comprising:
• obtained first metallization level performance-predictive parameter measurements data obtained from each of plural prior-tested IC chip samples during their manufacture and final performance metrics data associated with each said plural prior-tested IC sample after its manufacture, and said model using a complex power sorting criterion for IC performance classification, said complex power sorting criterion defining a non-linear power sort threshold as a function capturing a dependence between both the quiescent current (IDDQ) leakage power and the performance scaling ring oscillator (PSRO) delay in-line parametric measurements, the threshold defining a non-linear region for determining said final frequency and power product performance for said IC chip being manufactured;
• and
• in response to said determining, modifying a manufacturing step to optimize a manufacturing process to achieve a defined product performance specification for the IC chip being manufactured.