Processor with variable rate execution unit

A method of operating a processor having an execution unit that includes a first memory that holds data, a second memory that holds non-architectural instructions of a program, and a plurality of processing units, the method comprising:

• fetching and decoding, by a plurality of functional units of a processor, architectural instructions of an architectural instruction set of the processor at a first rate;
• programming into a register a value of an indicator, the value is programmable by execution of an architectural instruction of the architectural instruction set;
• executing, by the plurality of processing units, the non-architectural program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory;
• the non-architectural instructions are of an instruction set that is distinct from the architectural instruction set;
• and
• the second rate is the first rate when the indicator is programmed with a first predetermined value and the second rate is less than the first rate when the indicator is programmed with a second predetermined value.

A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

• computer usable program code embodied in said medium, for specifying a processor, the computer usable program code comprising:
• first program code for specifying a plurality of functional units that fetch and decode architectural instructions of an architectural instruction set of the processor at a first rate;
• second program code for specifying a register that stores a value of an indicator, the value is programmable by execution of an architectural instruction of the architectural instruction set;
• and
• third program code for specifying an execution unit, comprising:
• a first memory that holds data;
• a second memory that holds non-architectural instructions of a program, the non-architectural instructions are of an instruction set that is distinct from the architectural instruction set;
• a plurality of processing units that execute the non-architectural program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory;
• and
• the second rate is the first rate when the indicator is programmed with a first predetermined value and the second rate is less than the first rate when the indicator is programmed with a second predetermined value.